test/MC/AMDGPU/vop2.s

   1 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
   2 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
   3 // RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
   4 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=CIVI --check-prefix=VI
   5
   6 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI
   7 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI
   8 // RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI
   9 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck %s -check-prefix=NOVI
  10
  11 //===----------------------------------------------------------------------===//
  12 // Generic Checks for floating-point instructions (These have modifiers).
  13 //===----------------------------------------------------------------------===//
  14
  15 // TODO: 64-bit encoding of instructions with modifiers
  16
  17 // _e32 suffix
  18 // SICI: v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06]
  19 v_add_f32_e32 v1, v2, v3
  20
  21 // src0 inline immediate
  22 // SICI: v_add_f32_e32 v1, 1.0, v3 ; encoding: [0xf2,0x06,0x02,0x06]
  23 v_add_f32 v1, 1.0, v3
  24
  25 // src0 negative inline immediate
  26 // SICI: v_add_f32_e32 v1, -1.0, v3 ; encoding: [0xf3,0x06,0x02,0x06]
  27 v_add_f32 v1, -1.0, v3
  28
  29 // src0 literal
  30 // SICI: v_add_f32_e32 v1, 0x42c80000, v3 ; encoding: [0xff,0x06,0x02,0x06,0x00,0x00,0xc8,0x42]
  31 v_add_f32 v1, 100.0, v3
  32
  33 // src0 negative literal
  34 // SICI: v_add_f32_e32 v1, 0xc2c80000, v3 ; encoding: [0xff,0x06,0x02,0x06,0x00,0x00,0xc8,0xc2]
  35 v_add_f32 v1, -100.0, v3
  36
  37 //===----------------------------------------------------------------------===//
  38 // Generic Checks for integer instructions (These don't have modifiers).
  39 //===----------------------------------------------------------------------===//
  40
  41 // _e32 suffix
  42 // SICI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12]
  43 v_mul_i32_i24_e32 v1, v2, v3
  44
  45 // _e64 suffix
  46 // SICI: v_mul_i32_i24_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x02,0x00]
  47 v_mul_i32_i24_e64 v1, v2, v3
  48
  49 // src0 inline
  50 // SICI: v_mul_i32_i24_e32 v1, 3, v3 ; encoding: [0x83,0x06,0x02,0x12]
  51 v_mul_i32_i24_e32 v1, 3, v3
  52
  53 // src0 negative inline
  54 // SICI: v_mul_i32_i24_e32 v1, -3, v3 ; encoding: [0xc3,0x06,0x02,0x12]
  55 v_mul_i32_i24_e32 v1, -3, v3
  56
  57 // src1 inline
  58 // SICI: v_mul_i32_i24_e64 v1, v2, 3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x01,0x00]
  59 v_mul_i32_i24_e64 v1, v2, 3
  60
  61 // src1 negative inline
  62 // SICI: v_mul_i32_i24_e64 v1, v2, -3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x87,0x01,0x00]
  63 v_mul_i32_i24_e64 v1, v2, -3
  64
  65 // src0 literal
  66 // SICI: v_mul_i32_i24_e32 v1, 0x64, v3 ; encoding: [0xff,0x06,0x02,0x12,0x64,0x00,0x00,0x00]
  67 v_mul_i32_i24_e32 v1, 100, v3
  68
  69 // src1 negative literal
  70 // SICI: v_mul_i32_i24_e32 v1, 0xffffff9c, v3 ; encoding: [0xff,0x06,0x02,0x12,0x9c,0xff,0xff,0xff]
  71 v_mul_i32_i24_e32 v1, -100, v3
  72
  73 //===----------------------------------------------------------------------===//
  74 // Checks for legal operands
  75 //===----------------------------------------------------------------------===//
  76
  77 // src0 sgpr
  78 // SICI: v_mul_i32_i24_e32 v1, s2, v3 ; encoding: [0x02,0x06,0x02,0x12]
  79 v_mul_i32_i24_e32 v1, s2, v3
  80
  81 // src1 sgpr
  82 // SICI: v_mul_i32_i24_e64 v1, v2, s3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x00,0x00]
  83 v_mul_i32_i24_e64 v1, v2, s3
  84
  85 // src0, src1 same sgpr
  86 // SICI: v_mul_i32_i24_e64 v1, s2, s2 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x04,0x00,0x00]
  87 v_mul_i32_i24_e64 v1, s2, s2
  88
  89 // src0 sgpr, src1 inline
  90 // SICI: v_mul_i32_i24_e64 v1, s2, 3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x06,0x01,0x00]
  91 v_mul_i32_i24_e64 v1, s2, 3
  92
  93 // src0 inline src1 sgpr
  94 // SICI: v_mul_i32_i24_e64 v1, 3, s3 ; encoding: [0x01,0x00,0x12,0xd2,0x83,0x06,0x00,0x00]
  95 v_mul_i32_i24_e64 v1, 3, s3
  96
  97 // SICI: v_add_i32_e32 v0, vcc, 0.5, v0 ; encoding: [0xf0,0x00,0x00,0x4a]
  98 // NOVI: error: instruction not supported on this GPU
  99 v_add_i32_e32 v0, vcc, 0.5, v0
 100
 101 // SICI: v_add_i32_e32 v0, vcc, 0x40480000, v0 ; encoding: [0xff,0x00,0x00,0x4a,0x00,0x00,0x48,0x40]
 102 // NOVI: error: instruction not supported on this GPU
 103 v_add_i32_e32 v0, vcc, 3.125, v0
 104
 105 //===----------------------------------------------------------------------===//
 106 // Instructions
 107 //===----------------------------------------------------------------------===//
 108
 109 // GCN: v_cndmask_b32_e32 v1, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x00]
 110 v_cndmask_b32 v1, v2, v3, vcc
 111
 112 // GCN: v_cndmask_b32_e32 v1, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x00]
 113 v_cndmask_b32_e32 v1, v2, v3, vcc
 114
 115 // SICI: v_readlane_b32 s1, v2, s3 ; encoding: [0x02,0x07,0x02,0x02]
 116 // VI:   v_readlane_b32 s1, v2, s3 ; encoding: [0x01,0x00,0x89,0xd2,0x02,0x07,0x00,0x00]
 117 v_readlane_b32 s1, v2, s3
 118
 119 // SICI: v_writelane_b32 v1, s2, 4 ; encoding: [0x02,0x08,0x03,0x04]
 120 // VI:   v_writelane_b32 v1, s2, 4 ; encoding: [0x01,0x00,0x8a,0xd2,0x02,0x08,0x01,0x00]
 121 v_writelane_b32 v1, s2, 4
 122
 123 // SICI: v_writelane_b32 v2, 1, s4 ; encoding: [0x81,0x08,0x04,0x04]
 124 // VI:   v_writelane_b32 v2, 1, s4 ; encoding: [0x02,0x00,0x8a,0xd2,0x81,0x08,0x00,0x00]
 125 v_writelane_b32 v2, 1, s4
 126
 127 // SICI: v_writelane_b32 v255, 0xaf123456, 2 ; encoding: [0xff,0x04,0xff,0x05,0x56,0x34,0x12,0xaf]
 128 // NOVI: error: instruction not supported on this GPU
 129 v_writelane_b32 v255, 0xaf123456, 2
 130
 131 // SICI: v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06]
 132 // VI:   v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x02]
 133 v_add_f32 v1, v2, v3
 134
 135 // SICI: v_sub_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x08]
 136 // VI:   v_sub_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x04]
 137 v_sub_f32 v1, v2, v3
 138
 139 // SICI: v_subrev_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0a]
 140 // VI:   v_subrev_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06]
 141 v_subrev_f32 v1, v2, v3
 142
 143 // SICI: v_mac_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0c]
 144 // NOVI: error: instruction not supported on this GPU
 145 // NOVI: v_mac_legacy_f32 v1, v2, v3
 146 v_mac_legacy_f32 v1, v2, v3
 147
 148 // SICI: v_mul_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0e]
 149 // VI:   v_mul_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x08]
 150 v_mul_legacy_f32_e32 v1, v2, v3
 151
 152 // SICI: v_mul_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x10]
 153 // VI:   v_mul_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0a]
 154 v_mul_f32 v1, v2, v3
 155
 156 // SICI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12]
 157 // VI:   v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0c]
 158 v_mul_i32_i24_e32 v1, v2, v3
 159
 160 // SICI: v_mul_hi_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x14]
 161 // VI:   v_mul_hi_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0e]
 162 v_mul_hi_i32_i24_e32 v1, v2, v3
 163
 164 // SICI: v_mul_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x16]
 165 // VI:   v_mul_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x10]
 166 v_mul_u32_u24_e32 v1, v2, v3
 167
 168 // SICI: v_mul_hi_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x18]
 169 // VI:   v_mul_hi_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12]
 170 v_mul_hi_u32_u24_e32 v1, v2, v3
 171
 172 // SICI: v_min_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1a]
 173 // NOVI: error: instruction not supported on this GPU
 174 // NOVI: v_min_legacy_f32_e32 v1, v2, v3
 175 v_min_legacy_f32_e32 v1, v2, v3
 176
 177 // SICI: v_max_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1c]
 178 // NOVI: error: instruction not supported on this GPU
 179 // NOVI: v_max_legacy_f32 v1, v2, v3
 180 v_max_legacy_f32 v1, v2, v3
 181
 182 // SICI: v_min_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1e]
 183 // VI:   v_min_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x14]
 184 v_min_f32_e32 v1, v2, v3
 185
 186 // SICI: v_max_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x20]
 187 // VI:   v_max_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x16]
 188 v_max_f32 v1, v2 v3
 189
 190 // SICI: v_min_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x22]
 191 // VI:   v_min_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x18]
 192 v_min_i32_e32 v1, v2, v3
 193
 194 // SICI: v_max_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x24]
 195 // VI:   v_max_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1a]
 196 v_max_i32_e32 v1, v2, v3
 197
 198 // SICI: v_min_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x26]
 199 // VI:   v_min_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1c]
 200 v_min_u32_e32 v1, v2, v3
 201
 202 // SICI: v_max_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x28]
 203 // VI:   v_max_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1e]
 204 v_max_u32_e32 v1, v2, v3
 205
 206 // SICI: v_lshr_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2a]
 207 // NOVI: error: instruction not supported on this GPU
 208 // NOVI: v_lshr_b32_e32 v1, v2, v3
 209 v_lshr_b32_e32 v1, v2, v3
 210
 211 // SICI: v_lshrrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2c]
 212 // VI:   v_lshrrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x20]
 213 v_lshrrev_b32_e32 v1, v2, v3
 214
 215 // SICI: v_ashr_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2e]
 216 // NOVI: error: instruction not supported on this GPU
 217 // NOVI: v_ashr_i32_e32 v1, v2, v3
 218 v_ashr_i32_e32 v1, v2, v3
 219
 220 // SICI: v_ashrrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x30]
 221 // VI:   v_ashrrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x22]
 222 v_ashrrev_i32_e32 v1, v2, v3
 223
 224 // SICI: v_lshl_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x32]
 225 // NOVI: error: instruction not supported on this GPU
 226 // NOVI: v_lshl_b32_e32 v1, v2, v3
 227 v_lshl_b32_e32 v1, v2, v3
 228
 229 // SICI: v_lshlrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x34]
 230 // VI:   v_lshlrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x24]
 231 v_lshlrev_b32_e32 v1, v2, v3
 232
 233 // SICI: v_and_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x36]
 234 // VI:   v_and_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x26]
 235 v_and_b32_e32 v1, v2, v3
 236
 237 // SICI: v_or_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x38]
 238 // VI:   v_or_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x28]
 239 v_or_b32_e32 v1, v2, v3
 240
 241 // SICI: v_xor_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3a]
 242 // VI:   v_xor_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2a]
 243 v_xor_b32_e32 v1, v2, v3
 244
 245 // SICI: v_bfm_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x3c,0xd2,0x02,0x07,0x02,0x00]
 246 // VI:   v_bfm_b32 v1, v2, v3 ; encoding: [0x01,0x00,0x93,0xd2,0x02,0x07,0x02,0x00]
 247 v_bfm_b32_e64 v1, v2, v3
 248
 249 // SICI: v_mac_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3e]
 250 // VI:   v_mac_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2c]
 251 v_mac_f32_e32 v1, v2, v3
 252
 253 // SICI: v_madmk_f32 v1, v2, 0x42800000, v3 ; encoding: [0x02,0x07,0x02,0x40,0x00,0x00,0x80,0x42]
 254 // VI:   v_madmk_f32 v1, v2, 0x42800000, v3 ; encoding: [0x02,0x07,0x02,0x2e,0x00,0x00,0x80,0x42]
 255 v_madmk_f32 v1, v2, 64.0, v3
 256
 257 // SICI: v_madak_f32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x42,0x00,0x00,0x80,0x42]
 258 // VI:   v_madak_f32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x30,0x00,0x00,0x80,0x42]
 259 v_madak_f32 v1, v2, v3, 64.0
 260
 261 // SICI: v_bcnt_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x44,0xd2,0x02,0x07,0x02,0x00]
 262 // VI:   v_bcnt_u32_b32 v1, v2, v3 ; encoding: [0x01,0x00,0x8b,0xd2,0x02,0x07,0x02,0x00]
 263 v_bcnt_u32_b32_e64 v1, v2, v3
 264
 265 // SICI: v_mbcnt_lo_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x46,0xd2,0x02,0x07,0x02,0x00]
 266 // VI:   v_mbcnt_lo_u32_b32 v1, v2, v3 ; encoding: [0x01,0x00,0x8c,0xd2,0x02,0x07,0x02,0x00]
 267 v_mbcnt_lo_u32_b32_e64 v1, v2, v3
 268
 269 // SICI: v_mbcnt_hi_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x48,0xd2,0x02,0x07,0x02,0x00]
 270 // VI:   v_mbcnt_hi_u32_b32 v1, v2, v3 ; encoding: [0x01,0x00,0x8d,0xd2,0x02,0x07,0x02,0x00]
 271 v_mbcnt_hi_u32_b32_e64 v1, v2, v3
 272
 273 // SICI: v_add_i32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x4a]
 274 // NOVI: error: instruction not supported on this GPU
 275 v_add_i32_e32 v1, vcc, v2, v3
 276
 277 // SICI: v_add_i32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x4a,0xd2,0x02,0x07,0x02,0x00]
 278 // NOVI: error: instruction not supported on this GPU
 279 v_add_i32 v1, s[0:1], v2, v3
 280
 281 // SICI: v_add_i32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x4a,0xd2,0x02,0x07,0x02,0x00]
 282 // NOVI: error: instruction not supported on this GPU
 283 v_add_i32_e64 v1, s[0:1], v2, v3
 284
 285 // SICI: v_add_i32_e64 v1, vcc, v2, v3 ; encoding: [0x01,0x6a,0x4a,0xd2,0x02,0x07,0x02,0x00]
 286 // NOVI: error: instruction not supported on this GPU
 287 v_add_i32_e64 v1, vcc, v2, v3
 288
 289 // NOSICI: error: instruction not supported on this GPU
 290 // VI: v_add_u32_e32 v1, vcc, v2, v3   ; encoding: [0x02,0x07,0x02,0x32]
 291 v_add_u32 v1, vcc, v2, v3
 292
 293 // NOSICI: error: instruction not supported on this GPU
 294 // VI: v_add_u32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x19,0xd1,0x02,0x07,0x02,0x00]
 295 v_add_u32 v1, s[0:1], v2, v3
 296
 297 // SICI: v_sub_i32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x4c]
 298 // NOVI: error: instruction not supported on this GPU
 299 v_sub_i32 v1, vcc, v2, v3
 300
 301 // SICI: v_sub_i32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x4c,0xd2,0x02,0x07,0x02,0x00]
 302 // NOVI: error: instruction not supported on this GPU
 303 v_sub_i32 v1, s[0:1], v2, v3
 304
 305 // NOSICI: error: instruction not supported on this GPU
 306 // VI:   v_sub_u32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x34]
 307 v_sub_u32 v1, vcc, v2, v3
 308
 309 // NOSICI: error: instruction not supported on this GPU
 310 // VI:   v_sub_u32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x1a,0xd1,0x02,0x07,0x02,0x00]
 311 v_sub_u32 v1, s[0:1], v2, v3
 312
 313 // SICI: v_subrev_i32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x4e]
 314 // NOVI: error: instruction not supported on this GPU
 315 v_subrev_i32 v1, vcc, v2, v3
 316
 317 // SICI: v_subrev_i32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x4e,0xd2,0x02,0x07,0x02,0x00]
 318 // NOVI: error: instruction not supported on this GPU
 319 v_subrev_i32 v1, s[0:1], v2, v3
 320
 321 // NOSICI: error: instruction not supported on this GPU
 322 // VI:   v_subrev_u32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x36]
 323 v_subrev_u32 v1, vcc, v2, v3
 324
 325 // NOSICI: error: instruction not supported on this GPU
 326 // VI:   v_subrev_u32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x1b,0xd1,0x02,0x07,0x02,0x00]
 327 v_subrev_u32 v1, s[0:1], v2, v3
 328
 329 // SICI: v_addc_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x50]
 330 // VI:   v_addc_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x38]
 331 v_addc_u32 v1, vcc, v2, v3, vcc
 332
 333 // SICI: v_addc_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x50]
 334 // VI:   v_addc_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x38]
 335 v_addc_u32_e32 v1, vcc, v2, v3, vcc
 336
 337
 338 // SI: v_addc_u32_e64 v1, s[0:1], v2, v3, vcc ; encoding: [0x01,0x00,0x50,0xd2,0x02,0x07,0xaa,0x01]
 339 // VI: v_addc_u32_e64 v1, s[0:1], v2, v3, vcc ; encoding: [0x01,0x00,0x1c,0xd1,0x02,0x07,0xaa,0x01]
 340 v_addc_u32 v1, s[0:1], v2, v3, vcc
 341
 342 // SI: v_addc_u32_e64 v1, s[0:1], v2, v3, s[2:3] ; encoding: [0x01,0x00,0x50,0xd2,0x02,0x07,0x0a,0x00]
 343 // VI: v_addc_u32_e64 v1, s[0:1], v2, v3, s[2:3] ; encoding: [0x01,0x00,0x1c,0xd1,0x02,0x07,0x0a,0x00]
 344 v_addc_u32 v1, s[0:1], v2, v3, s[2:3]
 345
 346 // SI:  v_addc_u32_e64 v1, s[0:1], v2, v3, s[2:3] ; encoding: [0x01,0x00,0x50,0xd2,0x02,0x07,0x0a,0x00]
 347 // VI: v_addc_u32_e64 v1, s[0:1], v2, v3, s[2:3] ; encoding: [0x01,0x00,0x1c,0xd1,0x02,0x07,0x0a,0x00]
 348 v_addc_u32_e64 v1, s[0:1], v2, v3, s[2:3]
 349
 350 // SI: v_addc_u32_e64 v1, vcc, v2, v3, vcc ; encoding: [0x01,0x6a,0x50,0xd2,0x02,0x07,0xaa,0x01]
 351 // VI: v_addc_u32_e64 v1, vcc, v2, v3, vcc ; encoding: [0x01,0x6a,0x1c,0xd1,0x02,0x07,0xaa,0x01]
 352 v_addc_u32_e64 v1, vcc, v2, v3, vcc
 353
 354 // SI: v_subb_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x52]
 355 // VI: v_subb_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x3a]
 356 v_subb_u32 v1, vcc, v2, v3, vcc
 357
 358 // SI: v_subb_u32_e64 v1, s[0:1], v2, v3, vcc ; encoding: [0x01,0x00,0x52,0xd2,0x02,0x07,0xaa,0x01]
 359 // VI: v_subb_u32_e64 v1, s[0:1], v2, v3, vcc ; encoding: [0x01,0x00,0x1d,0xd1,0x02,0x07,0xaa,0x01]
 360 v_subb_u32 v1, s[0:1], v2, v3, vcc
 361
 362 // SICI: v_subbrev_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x54]
 363 // VI:   v_subbrev_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x3c]
 364 v_subbrev_u32 v1, vcc, v2, v3, vcc
 365
 366 // SICI: v_subbrev_u32_e64 v1, s[0:1], v2, v3, vcc ; encoding: [0x01,0x00,0x54,0xd2,0x02,0x07,0xaa,0x01]
 367 // VI: v_subbrev_u32_e64 v1, s[0:1], v2, v3, vcc ; encoding: [0x01,0x00,0x1e,0xd1,0x02,0x07,0xaa,0x01]
 368 v_subbrev_u32 v1, s[0:1], v2, v3, vcc
 369
 370 // SICI: v_ldexp_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56]
 371 // VI:   v_ldexp_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x88,0xd2,0x02,0x07,0x02,0x00]
 372 v_ldexp_f32 v1, v2, v3
 373
 374 // SICI: v_cvt_pkaccum_u8_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58]
 375 // VI:   v_cvt_pkaccum_u8_f32 v1, v2, v3 ; encoding: [0x01,0x00,0xf0,0xd1,0x02,0x07,0x02,0x00]
 376 v_cvt_pkaccum_u8_f32 v1, v2, v3
 377
 378 // SICI: v_cvt_pknorm_i16_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a]
 379 // VI:   v_cvt_pknorm_i16_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x94,0xd2,0x02,0x07,0x02,0x00]
 380 v_cvt_pknorm_i16_f32 v1, v2, v3
 381
 382 // SICI: v_cvt_pknorm_u16_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5c]
 383 // VI:   v_cvt_pknorm_u16_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x95,0xd2,0x02,0x07,0x02,0x00]
 384 v_cvt_pknorm_u16_f32 v1, v2, v3
 385
 386 // SICI: v_cvt_pkrtz_f16_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5e]
 387 // VI:   v_cvt_pkrtz_f16_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x96,0xd2,0x02,0x07,0x02,0x00]
 388 v_cvt_pkrtz_f16_f32 v1, v2, v3
 389
 390 // SICI: v_cvt_pk_u16_u32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x60,0xd2,0x02,0x07,0x02,0x00]
 391 // VI:   v_cvt_pk_u16_u32 v1, v2, v3 ; encoding: [0x01,0x00,0x97,0xd2,0x02,0x07,0x02,0x00]
 392 v_cvt_pk_u16_u32_e64 v1, v2, v3
 393
 394 // SICI: v_cvt_pk_i16_i32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x62,0xd2,0x02,0x07,0x02,0x00]
 395 // VI:   v_cvt_pk_i16_i32 v1, v2, v3 ; encoding: [0x01,0x00,0x98,0xd2,0x02,0x07,0x02,0x00]
 396 v_cvt_pk_i16_i32_e64 v1, v2, v3
 397
 398 // NOSICI: error: instruction not supported on this GPU
 399 // NOSICI: v_add_f16_e32 v1, v2, v3
 400 // VI:     v_add_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3e]
 401 v_add_f16_e32 v1, v2, v3
 402
 403 // NOSICI: error: instruction not supported on this GPU
 404 // NOSICI: v_sub_f16_e32 v1, v2, v3
 405 // VI:     v_sub_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x40]
 406 v_sub_f16_e32 v1, v2, v3
 407
 408 // NOSICI: error: instruction not supported on this GPU
 409 // NOSICI: v_subrev_f16_e32 v1, v2, v3
 410 // VI:     v_subrev_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x42]
 411 v_subrev_f16_e32 v1, v2, v3
 412
 413 // NOSICI: error: instruction not supported on this GPU
 414 // NOSICI: v_mul_f16_e32 v1, v2, v3
 415 // VI:     v_mul_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x44]
 416 v_mul_f16_e32 v1, v2, v3
 417
 418 // NOSICI: error: instruction not supported on this GPU
 419 // NOSICI: v_mac_f16_e32 v1, v2, v3
 420 // VI:     v_mac_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x46]
 421 v_mac_f16_e32 v1, v2, v3
 422
 423 // NOSICI: error: instruction not supported on this GPU
 424 // NOSICI: v_madmk_f16 v1, v2, 64.0, v3
 425 // VI:     v_madmk_f16 v1, v2, 0x5400, v3 ; encoding: [0x02,0x07,0x02,0x48,0x00,0x54,0x00,0x00]
 426 v_madmk_f16 v1, v2, 64.0, v3
 427
 428 // NOSICI: error: instruction not supported on this GPU
 429 // NOSICI: v_madak_f16 v1, v2, v3, 64.0
 430 // VI:     v_madak_f16 v1, v2, v3, 0x5400 ; encoding: [0x02,0x07,0x02,0x4a,0x00,0x54,0x00,0x00]
 431 v_madak_f16 v1, v2, v3, 64.0
 432
 433 // NOSICI: error: instruction not supported on this GPU
 434 // NOSICI: v_add_u16_e32 v1, v2, v3
 435 // VI:     v_add_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4c]
 436 v_add_u16_e32 v1, v2, v3
 437
 438 // NOSICI: error: instruction not supported on this GPU
 439 // NOSICI: v_sub_u16_e32 v1, v2, v3
 440 // VI:     v_sub_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4e]
 441 v_sub_u16_e32 v1, v2, v3
 442
 443 // NOSICI: error: instruction not supported on this GPU
 444 // NOSICI: v_subrev_u16_e32 v1, v2, v3
 445 // VI:     v_subrev_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x50]
 446 v_subrev_u16_e32 v1, v2, v3
 447
 448 // NOSICI: error: instruction not supported on this GPU
 449 // NOSICI: v_mul_lo_u16_e32 v1, v2, v3
 450 // VI:     v_mul_lo_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x52]
 451 v_mul_lo_u16_e32 v1, v2, v3
 452
 453 // NOSICI: error: instruction not supported on this GPU
 454 // NOSICI: v_lshlrev_b16_e32 v1, v2, v3
 455 // VI:     v_lshlrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x54]
 456 v_lshlrev_b16_e32 v1, v2, v3
 457
 458 // NOSICI: error: instruction not supported on this GPU
 459 // NOSICI: v_lshrrev_b16_e32 v1, v2, v3
 460 // VI: v_lshrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56]
 461 v_lshrrev_b16_e32 v1, v2, v3
 462
 463 // NOSICI: error: instruction not supported on this GPU
 464 // NOSICI: v_ashrrev_i16_e32 v1, v2, v3
 465 // VI:     v_ashrrev_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58]
 466 v_ashrrev_i16_e32 v1, v2, v3
 467
 468 // NOSICI: error: instruction not supported on this GPU
 469 // NOSICI: v_max_f16_e32 v1, v2, v3
 470 // VI:     v_max_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a]
 471 v_max_f16_e32 v1, v2, v3
 472
 473 // NOSICI: error: instruction not supported on this GPU
 474 // NOSICI: v_min_f16_e32 v1, v2, v3
 475 // VI:     v_min_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5c]
 476 v_min_f16_e32 v1, v2, v3
 477
 478 // NOSICI: error: instruction not supported on this GPU
 479 // NOSICI: v_max_u16_e32 v1, v2, v3
 480 // VI:     v_max_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5e]
 481 v_max_u16_e32 v1, v2, v3
 482
 483 // NOSICI: error: instruction not supported on this GPU
 484 // NOSICI: v_max_i16_e32 v1, v2, v3
 485 // VI:     v_max_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x60]
 486 v_max_i16_e32 v1, v2, v3
 487
 488 // NOSICI: error: instruction not supported on this GPU
 489 // NOSICI: v_min_u16_e32 v1, v2, v3
 490 // VI:     v_min_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x62]
 491 v_min_u16_e32 v1, v2, v3
 492
 493 // NOSICI: error: instruction not supported on this GPU
 494 // NOSICI: v_min_i16_e32 v1, v2, v3
 495 // VI:     v_min_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x64]
 496 v_min_i16_e32 v1, v2, v3
 497
 498 // NOSICI: error: instruction not supported on this GPU
 499 // NOSICI: v_ldexp_f16_e32 v1, v2, v3
 500 // VI:     v_ldexp_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x66]
 501 v_ldexp_f16_e32 v1, v2, v3