1 // RUN
: llvm-mc
-arch
=amdgcn
-mcpu
=gfx908
-show-encoding
%s | FileCheck
%s
3 // CHECK
: encoding
: [0x01,0x05,0x0a,0x6e]
4 v_dot2c_f32_f16 v5
, v1
, v2
6 // CHECK
: encoding
: [0x01,0x05,0xfe,0x6f]
7 v_dot2c_f32_f16 v255
, v1
, v2
9 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x00,0x00]
10 v_dot2c_f32_f16_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
12 // CHECK
: encoding
: [0xfa,0x04,0xfe,0x6f,0x01,0xe4,0x00,0x00]
13 v_dot2c_f32_f16_dpp v255
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
15 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0xff,0xe4,0x00,0x00]
16 v_dot2c_f32_f16_dpp v5
, v255
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
18 // CHECK
: encoding
: [0xfa,0xfe,0x0b,0x6e,0x01,0xe4,0x00,0x00]
19 v_dot2c_f32_f16_dpp v5
, v1
, v255 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
21 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0x1b,0x00,0x00]
22 v_dot2c_f32_f16_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0] row_mask
:0x0 bank_mask
:0x0
24 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0x40,0x01,0x00]
25 v_dot2c_f32_f16_dpp v5
, v1
, v2 row_mirror row_mask
:0x0 bank_mask
:0x0
27 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0x41,0x01,0x00]
28 v_dot2c_f32_f16_dpp v5
, v1
, v2 row_half_mirror row_mask
:0x0 bank_mask
:0x0
30 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0x42,0x01,0x00]
31 v_dot2c_f32_f16_dpp v5
, v1
, v2 row_bcast
:15 row_mask
:0x0 bank_mask
:0x0
33 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0x43,0x01,0x00]
34 v_dot2c_f32_f16_dpp v5
, v1
, v2 row_bcast
:31 row_mask
:0x0 bank_mask
:0x0
36 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0x30,0x01,0x00]
37 v_dot2c_f32_f16_dpp v5
, v1
, v2 wave_shl
:1 row_mask
:0x0 bank_mask
:0x0
39 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0x34,0x01,0x00]
40 v_dot2c_f32_f16_dpp v5
, v1
, v2 wave_rol
:1 row_mask
:0x0 bank_mask
:0x0
42 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0x38,0x01,0x00]
43 v_dot2c_f32_f16_dpp v5
, v1
, v2 wave_shr
:1 row_mask
:0x0 bank_mask
:0x0
45 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0x3c,0x01,0x00]
46 v_dot2c_f32_f16_dpp v5
, v1
, v2 wave_ror
:1 row_mask
:0x0 bank_mask
:0x0
48 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0x01,0x01,0x00]
49 v_dot2c_f32_f16_dpp v5
, v1
, v2 row_shl
:1 row_mask
:0x0 bank_mask
:0x0
51 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0x0f,0x01,0x00]
52 v_dot2c_f32_f16_dpp v5
, v1
, v2 row_shl
:15 row_mask
:0x0 bank_mask
:0x0
54 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0x11,0x01,0x00]
55 v_dot2c_f32_f16_dpp v5
, v1
, v2 row_shr
:1 row_mask
:0x0 bank_mask
:0x0
57 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0x1f,0x01,0x00]
58 v_dot2c_f32_f16_dpp v5
, v1
, v2 row_shr
:15 row_mask
:0x0 bank_mask
:0x0
60 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0x21,0x01,0x00]
61 v_dot2c_f32_f16_dpp v5
, v1
, v2 row_ror
:1 row_mask
:0x0 bank_mask
:0x0
63 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0x2f,0x01,0x00]
64 v_dot2c_f32_f16_dpp v5
, v1
, v2 row_ror
:15 row_mask
:0x0 bank_mask
:0x0
66 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x00,0x10]
67 v_dot2c_f32_f16_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x1 bank_mask
:0x0
69 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x00,0x30]
70 v_dot2c_f32_f16_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x3 bank_mask
:0x0
72 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x00,0xf0]
73 v_dot2c_f32_f16_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0xf bank_mask
:0x0
75 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x00,0xf0]
76 v_dot2c_f32_f16_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] bank_mask
:0x0
78 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x00,0x01]
79 v_dot2c_f32_f16_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x1
81 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x00,0x03]
82 v_dot2c_f32_f16_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x3
84 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x00,0x0f]
85 v_dot2c_f32_f16_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0xf
87 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x00,0x0f]
88 v_dot2c_f32_f16_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0
90 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x08,0x00]
91 v_dot2c_f32_f16_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0 bound_ctrl
:0
93 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x10,0x00]
94 v_dot2c_f32_f16_dpp v5
, -v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
96 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x20,0x00]
97 v_dot2c_f32_f16_dpp v5
, |v1|
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
99 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x40,0x00]
100 v_dot2c_f32_f16_dpp v5
, v1
, -v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
102 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x80,0x00]
103 v_dot2c_f32_f16_dpp v5
, v1
, |v2| quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
105 // CHECK
: encoding
: [0x01,0x05,0x0a,0x70]
106 v_dot2c_i32_i16 v5
, v1
, v2
108 // CHECK
: encoding
: [0x01,0x05,0xfe,0x71]
109 v_dot2c_i32_i16 v255
, v1
, v2
111 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0xe4,0x00,0x00]
112 v_dot2c_i32_i16_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
114 // CHECK
: encoding
: [0xfa,0x04,0xfe,0x71,0x01,0xe4,0x00,0x00]
115 v_dot2c_i32_i16_dpp v255
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
117 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0xff,0xe4,0x00,0x00]
118 v_dot2c_i32_i16_dpp v5
, v255
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
120 // CHECK
: encoding
: [0xfa,0xfe,0x0b,0x70,0x01,0xe4,0x00,0x00]
121 v_dot2c_i32_i16_dpp v5
, v1
, v255 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
123 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0x1b,0x00,0x00]
124 v_dot2c_i32_i16_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0] row_mask
:0x0 bank_mask
:0x0
126 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0x40,0x01,0x00]
127 v_dot2c_i32_i16_dpp v5
, v1
, v2 row_mirror row_mask
:0x0 bank_mask
:0x0
129 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0x41,0x01,0x00]
130 v_dot2c_i32_i16_dpp v5
, v1
, v2 row_half_mirror row_mask
:0x0 bank_mask
:0x0
132 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0x42,0x01,0x00]
133 v_dot2c_i32_i16_dpp v5
, v1
, v2 row_bcast
:15 row_mask
:0x0 bank_mask
:0x0
135 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0x43,0x01,0x00]
136 v_dot2c_i32_i16_dpp v5
, v1
, v2 row_bcast
:31 row_mask
:0x0 bank_mask
:0x0
138 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0x30,0x01,0x00]
139 v_dot2c_i32_i16_dpp v5
, v1
, v2 wave_shl
:1 row_mask
:0x0 bank_mask
:0x0
141 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0x34,0x01,0x00]
142 v_dot2c_i32_i16_dpp v5
, v1
, v2 wave_rol
:1 row_mask
:0x0 bank_mask
:0x0
144 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0x38,0x01,0x00]
145 v_dot2c_i32_i16_dpp v5
, v1
, v2 wave_shr
:1 row_mask
:0x0 bank_mask
:0x0
147 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0x3c,0x01,0x00]
148 v_dot2c_i32_i16_dpp v5
, v1
, v2 wave_ror
:1 row_mask
:0x0 bank_mask
:0x0
150 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0x01,0x01,0x00]
151 v_dot2c_i32_i16_dpp v5
, v1
, v2 row_shl
:1 row_mask
:0x0 bank_mask
:0x0
153 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0x0f,0x01,0x00]
154 v_dot2c_i32_i16_dpp v5
, v1
, v2 row_shl
:15 row_mask
:0x0 bank_mask
:0x0
156 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0x11,0x01,0x00]
157 v_dot2c_i32_i16_dpp v5
, v1
, v2 row_shr
:1 row_mask
:0x0 bank_mask
:0x0
159 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0x1f,0x01,0x00]
160 v_dot2c_i32_i16_dpp v5
, v1
, v2 row_shr
:15 row_mask
:0x0 bank_mask
:0x0
162 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0x21,0x01,0x00]
163 v_dot2c_i32_i16_dpp v5
, v1
, v2 row_ror
:1 row_mask
:0x0 bank_mask
:0x0
165 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0x2f,0x01,0x00]
166 v_dot2c_i32_i16_dpp v5
, v1
, v2 row_ror
:15 row_mask
:0x0 bank_mask
:0x0
168 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0xe4,0x00,0x10]
169 v_dot2c_i32_i16_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x1 bank_mask
:0x0
171 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0xe4,0x00,0x30]
172 v_dot2c_i32_i16_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x3 bank_mask
:0x0
174 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0xe4,0x00,0xf0]
175 v_dot2c_i32_i16_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0xf bank_mask
:0x0
177 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0xe4,0x00,0xf0]
178 v_dot2c_i32_i16_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] bank_mask
:0x0
180 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0xe4,0x00,0x01]
181 v_dot2c_i32_i16_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x1
183 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0xe4,0x00,0x03]
184 v_dot2c_i32_i16_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x3
186 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0xe4,0x00,0x0f]
187 v_dot2c_i32_i16_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0xf
189 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0xe4,0x00,0x0f]
190 v_dot2c_i32_i16_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0
192 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x70,0x01,0xe4,0x08,0x00]
193 v_dot2c_i32_i16_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0 bound_ctrl
:0
195 // CHECK
: encoding
: [0x01,0x05,0x0a,0x72]
196 v_dot4c_i32_i8 v5
, v1
, v2
198 // CHECK
: encoding
: [0x01,0x05,0xfe,0x73]
199 v_dot4c_i32_i8 v255
, v1
, v2
201 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x00]
202 v_dot4c_i32_i8_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
204 // CHECK
: encoding
: [0xfa,0x04,0xfe,0x73,0x01,0xe4,0x00,0x00]
205 v_dot4c_i32_i8_dpp v255
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
207 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0xff,0xe4,0x00,0x00]
208 v_dot4c_i32_i8_dpp v5
, v255
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
210 // CHECK
: encoding
: [0xfa,0xfe,0x0b,0x72,0x01,0xe4,0x00,0x00]
211 v_dot4c_i32_i8_dpp v5
, v1
, v255 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
213 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0x1b,0x00,0x00]
214 v_dot4c_i32_i8_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0] row_mask
:0x0 bank_mask
:0x0
216 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0x40,0x01,0x00]
217 v_dot4c_i32_i8_dpp v5
, v1
, v2 row_mirror row_mask
:0x0 bank_mask
:0x0
219 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0x41,0x01,0x00]
220 v_dot4c_i32_i8_dpp v5
, v1
, v2 row_half_mirror row_mask
:0x0 bank_mask
:0x0
222 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0x42,0x01,0x00]
223 v_dot4c_i32_i8_dpp v5
, v1
, v2 row_bcast
:15 row_mask
:0x0 bank_mask
:0x0
225 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0x43,0x01,0x00]
226 v_dot4c_i32_i8_dpp v5
, v1
, v2 row_bcast
:31 row_mask
:0x0 bank_mask
:0x0
228 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0x30,0x01,0x00]
229 v_dot4c_i32_i8_dpp v5
, v1
, v2 wave_shl
:1 row_mask
:0x0 bank_mask
:0x0
231 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0x34,0x01,0x00]
232 v_dot4c_i32_i8_dpp v5
, v1
, v2 wave_rol
:1 row_mask
:0x0 bank_mask
:0x0
234 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0x38,0x01,0x00]
235 v_dot4c_i32_i8_dpp v5
, v1
, v2 wave_shr
:1 row_mask
:0x0 bank_mask
:0x0
237 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0x3c,0x01,0x00]
238 v_dot4c_i32_i8_dpp v5
, v1
, v2 wave_ror
:1 row_mask
:0x0 bank_mask
:0x0
240 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0x01,0x01,0x00]
241 v_dot4c_i32_i8_dpp v5
, v1
, v2 row_shl
:1 row_mask
:0x0 bank_mask
:0x0
243 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0x0f,0x01,0x00]
244 v_dot4c_i32_i8_dpp v5
, v1
, v2 row_shl
:15 row_mask
:0x0 bank_mask
:0x0
246 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0x11,0x01,0x00]
247 v_dot4c_i32_i8_dpp v5
, v1
, v2 row_shr
:1 row_mask
:0x0 bank_mask
:0x0
249 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0x1f,0x01,0x00]
250 v_dot4c_i32_i8_dpp v5
, v1
, v2 row_shr
:15 row_mask
:0x0 bank_mask
:0x0
252 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0x21,0x01,0x00]
253 v_dot4c_i32_i8_dpp v5
, v1
, v2 row_ror
:1 row_mask
:0x0 bank_mask
:0x0
255 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0x2f,0x01,0x00]
256 v_dot4c_i32_i8_dpp v5
, v1
, v2 row_ror
:15 row_mask
:0x0 bank_mask
:0x0
258 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x10]
259 v_dot4c_i32_i8_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x1 bank_mask
:0x0
261 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x30]
262 v_dot4c_i32_i8_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x3 bank_mask
:0x0
264 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0xf0]
265 v_dot4c_i32_i8_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0xf bank_mask
:0x0
267 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0xf0]
268 v_dot4c_i32_i8_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] bank_mask
:0x0
270 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x01]
271 v_dot4c_i32_i8_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x1
273 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x03]
274 v_dot4c_i32_i8_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x3
276 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x0f]
277 v_dot4c_i32_i8_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0xf
279 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x0f]
280 v_dot4c_i32_i8_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0
282 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x08,0x00]
283 v_dot4c_i32_i8_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0 bound_ctrl
:0
285 // CHECK
: encoding
: [0x01,0x05,0x0a,0x74]
286 v_dot8c_i32_i4 v5
, v1
, v2
288 // CHECK
: encoding
: [0x01,0x05,0xfe,0x75]
289 v_dot8c_i32_i4 v255
, v1
, v2
291 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x00]
292 v_dot8c_i32_i4_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
294 // CHECK
: encoding
: [0xfa,0x04,0xfe,0x75,0x01,0xe4,0x00,0x00]
295 v_dot8c_i32_i4_dpp v255
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
297 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0xff,0xe4,0x00,0x00]
298 v_dot8c_i32_i4_dpp v5
, v255
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
300 // CHECK
: encoding
: [0xfa,0xfe,0x0b,0x74,0x01,0xe4,0x00,0x00]
301 v_dot8c_i32_i4_dpp v5
, v1
, v255 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
303 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0x1b,0x00,0x00]
304 v_dot8c_i32_i4_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0] row_mask
:0x0 bank_mask
:0x0
306 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0x40,0x01,0x00]
307 v_dot8c_i32_i4_dpp v5
, v1
, v2 row_mirror row_mask
:0x0 bank_mask
:0x0
309 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0x41,0x01,0x00]
310 v_dot8c_i32_i4_dpp v5
, v1
, v2 row_half_mirror row_mask
:0x0 bank_mask
:0x0
312 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0x42,0x01,0x00]
313 v_dot8c_i32_i4_dpp v5
, v1
, v2 row_bcast
:15 row_mask
:0x0 bank_mask
:0x0
315 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0x43,0x01,0x00]
316 v_dot8c_i32_i4_dpp v5
, v1
, v2 row_bcast
:31 row_mask
:0x0 bank_mask
:0x0
318 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0x30,0x01,0x00]
319 v_dot8c_i32_i4_dpp v5
, v1
, v2 wave_shl
:1 row_mask
:0x0 bank_mask
:0x0
321 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0x34,0x01,0x00]
322 v_dot8c_i32_i4_dpp v5
, v1
, v2 wave_rol
:1 row_mask
:0x0 bank_mask
:0x0
324 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0x38,0x01,0x00]
325 v_dot8c_i32_i4_dpp v5
, v1
, v2 wave_shr
:1 row_mask
:0x0 bank_mask
:0x0
327 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0x3c,0x01,0x00]
328 v_dot8c_i32_i4_dpp v5
, v1
, v2 wave_ror
:1 row_mask
:0x0 bank_mask
:0x0
330 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0x01,0x01,0x00]
331 v_dot8c_i32_i4_dpp v5
, v1
, v2 row_shl
:1 row_mask
:0x0 bank_mask
:0x0
333 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0x0f,0x01,0x00]
334 v_dot8c_i32_i4_dpp v5
, v1
, v2 row_shl
:15 row_mask
:0x0 bank_mask
:0x0
336 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0x11,0x01,0x00]
337 v_dot8c_i32_i4_dpp v5
, v1
, v2 row_shr
:1 row_mask
:0x0 bank_mask
:0x0
339 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0x1f,0x01,0x00]
340 v_dot8c_i32_i4_dpp v5
, v1
, v2 row_shr
:15 row_mask
:0x0 bank_mask
:0x0
342 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0x21,0x01,0x00]
343 v_dot8c_i32_i4_dpp v5
, v1
, v2 row_ror
:1 row_mask
:0x0 bank_mask
:0x0
345 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0x2f,0x01,0x00]
346 v_dot8c_i32_i4_dpp v5
, v1
, v2 row_ror
:15 row_mask
:0x0 bank_mask
:0x0
348 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x10]
349 v_dot8c_i32_i4_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x1 bank_mask
:0x0
351 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x30]
352 v_dot8c_i32_i4_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x3 bank_mask
:0x0
354 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0xf0]
355 v_dot8c_i32_i4_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0xf bank_mask
:0x0
357 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0xf0]
358 v_dot8c_i32_i4_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] bank_mask
:0x0
360 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x01]
361 v_dot8c_i32_i4_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x1
363 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x03]
364 v_dot8c_i32_i4_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x3
366 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x0f]
367 v_dot8c_i32_i4_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0xf
369 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x0f]
370 v_dot8c_i32_i4_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0
372 // CHECK
: encoding
: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x08,0x00]
373 v_dot8c_i32_i4_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0 bound_ctrl
:0
375 // CHECK
: encoding
: [0x01,0x05,0x0a,0x78]
376 v_pk_fmac_f16 v5
, v1
, v2
378 // CHECK
: encoding
: [0x01,0x05,0xfe,0x79]
379 v_pk_fmac_f16 v255
, v1
, v2
381 // CHECK
: encoding
: [0xff,0x05,0x0a,0x78]
382 v_pk_fmac_f16 v5
, v255
, v2
384 // CHECK
: encoding
: [0x01,0x04,0x0a,0x78]
385 v_pk_fmac_f16 v5
, s1
, v2
387 // CHECK
: encoding
: [0x6a,0x04,0x0a,0x78]
388 v_pk_fmac_f16 v5
, vcc_lo
, v2
390 // CHECK
: encoding
: [0x6b,0x04,0x0a,0x78]
391 v_pk_fmac_f16 v5
, vcc_hi
, v2
393 // CHECK
: encoding
: [0x77,0x04,0x0a,0x78]
394 v_pk_fmac_f16 v5
, ttmp11
, v2
396 // CHECK
: encoding
: [0x7c,0x04,0x0a,0x78]
397 v_pk_fmac_f16 v5
, m0
, v2
399 // CHECK
: encoding
: [0x7e,0x04,0x0a,0x78]
400 v_pk_fmac_f16 v5
, exec_lo
, v2
402 // CHECK
: encoding
: [0x7f,0x04,0x0a,0x78]
403 v_pk_fmac_f16 v5
, exec_hi
, v2
405 // CHECK
: encoding
: [0x80,0x04,0x0a,0x78]
406 v_pk_fmac_f16 v5
, 0, v2
408 // CHECK
: encoding
: [0xc1,0x04,0x0a,0x78]
409 v_pk_fmac_f16 v5
, -1, v2
411 // CHECK
: encoding
: [0xf0,0x04,0x0a,0x78]
412 v_pk_fmac_f16 v5
, 0.5, v2
414 // CHECK
: encoding
: [0xf7,0x04,0x0a,0x78]
415 v_pk_fmac_f16 v5
, -4.0, v2
417 // CHECK
: encoding
: [0x01,0xff,0x0b,0x78]
418 v_pk_fmac_f16 v5
, v1
, v255