| blob | 846d97d550736da427b45e19ffce126881891056 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X32
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X64
5 define <2 x double> @signbits_sext_v2i64_sitofp_v2f64(i32 %a0, i32 %a1) nounwind {
6 ; X32-LABEL: signbits_sext_v2i64_sitofp_v2f64:
7 ; X32: # %bb.0:
8 ; X32-NEXT: vcvtdq2pd {{[0-9]+}}(%esp), %xmm0
9 ; X32-NEXT: retl
10 ;
11 ; X64-LABEL: signbits_sext_v2i64_sitofp_v2f64:
12 ; X64: # %bb.0:
13 ; X64-NEXT: vmovd %edi, %xmm0
14 ; X64-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0
15 ; X64-NEXT: vcvtdq2pd %xmm0, %xmm0
16 ; X64-NEXT: retq
17 %1 = sext i32 %a0 to i64
18 %2 = sext i32 %a1 to i64
19 %3 = insertelement <2 x i64> undef, i64 %1, i32 0
20 %4 = insertelement <2 x i64> %3, i64 %2, i32 1
21 %5 = sitofp <2 x i64> %4 to <2 x double>
22 ret <2 x double> %5
23 }
25 define <4 x float> @signbits_sext_v4i64_sitofp_v4f32(i8 signext %a0, i16 signext %a1, i32 %a2, i32 %a3) nounwind {
26 ; X32-LABEL: signbits_sext_v4i64_sitofp_v4f32:
27 ; X32: # %bb.0:
28 ; X32-NEXT: movswl {{[0-9]+}}(%esp), %eax
29 ; X32-NEXT: movsbl {{[0-9]+}}(%esp), %ecx
30 ; X32-NEXT: vmovd %ecx, %xmm0
31 ; X32-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0
32 ; X32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
33 ; X32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
34 ; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
35 ; X32-NEXT: retl
36 ;
37 ; X64-LABEL: signbits_sext_v4i64_sitofp_v4f32:
38 ; X64: # %bb.0:
39 ; X64-NEXT: vmovd %edi, %xmm0
40 ; X64-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0
41 ; X64-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0
42 ; X64-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0
43 ; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
44 ; X64-NEXT: retq
45 %1 = sext i8 %a0 to i64
46 %2 = sext i16 %a1 to i64
47 %3 = sext i32 %a2 to i64
48 %4 = sext i32 %a3 to i64
49 %5 = insertelement <4 x i64> undef, i64 %1, i32 0
50 %6 = insertelement <4 x i64> %5, i64 %2, i32 1
51 %7 = insertelement <4 x i64> %6, i64 %3, i32 2
52 %8 = insertelement <4 x i64> %7, i64 %4, i32 3
53 %9 = sitofp <4 x i64> %8 to <4 x float>
54 ret <4 x float> %9
55 }
57 define float @signbits_ashr_extract_sitofp_0(<2 x i64> %a0) nounwind {
58 ; X32-LABEL: signbits_ashr_extract_sitofp_0:
59 ; X32: # %bb.0:
60 ; X32-NEXT: pushl %eax
61 ; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,1,2,3]
62 ; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
63 ; X32-NEXT: vmovss %xmm0, (%esp)
64 ; X32-NEXT: flds (%esp)
65 ; X32-NEXT: popl %eax
66 ; X32-NEXT: retl
67 ;
68 ; X64-LABEL: signbits_ashr_extract_sitofp_0:
69 ; X64: # %bb.0:
70 ; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,1,2,3]
71 ; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
72 ; X64-NEXT: retq
73 %1 = ashr <2 x i64> %a0, <i64 32, i64 32>
74 %2 = extractelement <2 x i64> %1, i32 0
75 %3 = sitofp i64 %2 to float
76 ret float %3
77 }
79 define float @signbits_ashr_extract_sitofp_1(<2 x i64> %a0) nounwind {
80 ; X32-LABEL: signbits_ashr_extract_sitofp_1:
81 ; X32: # %bb.0:
82 ; X32-NEXT: pushl %eax
83 ; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,1,2,3]
84 ; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
85 ; X32-NEXT: vmovss %xmm0, (%esp)
86 ; X32-NEXT: flds (%esp)
87 ; X32-NEXT: popl %eax
88 ; X32-NEXT: retl
89 ;
90 ; X64-LABEL: signbits_ashr_extract_sitofp_1:
91 ; X64: # %bb.0:
92 ; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,1,2,3]
93 ; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
94 ; X64-NEXT: retq
95 %1 = ashr <2 x i64> %a0, <i64 32, i64 63>
96 %2 = extractelement <2 x i64> %1, i32 0
97 %3 = sitofp i64 %2 to float
98 ret float %3
99 }
101 define float @signbits_ashr_shl_extract_sitofp(<2 x i64> %a0) nounwind {
102 ; X32-LABEL: signbits_ashr_shl_extract_sitofp:
103 ; X32: # %bb.0:
104 ; X32-NEXT: pushl %eax
105 ; X32-NEXT: vpsrad $29, %xmm0, %xmm0
106 ; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
107 ; X32-NEXT: vpsllq $20, %xmm0, %xmm0
108 ; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
109 ; X32-NEXT: vmovss %xmm0, (%esp)
110 ; X32-NEXT: flds (%esp)
111 ; X32-NEXT: popl %eax
112 ; X32-NEXT: retl
113 ;
114 ; X64-LABEL: signbits_ashr_shl_extract_sitofp:
115 ; X64: # %bb.0:
116 ; X64-NEXT: vpsrad $29, %xmm0, %xmm0
117 ; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
118 ; X64-NEXT: vpsllq $20, %xmm0, %xmm0
119 ; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
120 ; X64-NEXT: retq
121 %1 = ashr <2 x i64> %a0, <i64 61, i64 60>
122 %2 = shl <2 x i64> %1, <i64 20, i64 16>
123 %3 = extractelement <2 x i64> %2, i32 0
124 %4 = sitofp i64 %3 to float
125 ret float %4
126 }
128 define float @signbits_ashr_insert_ashr_extract_sitofp(i64 %a0, i64 %a1) nounwind {
129 ; X32-LABEL: signbits_ashr_insert_ashr_extract_sitofp:
130 ; X32: # %bb.0:
131 ; X32-NEXT: pushl %eax
132 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
133 ; X32-NEXT: movl %eax, %ecx
134 ; X32-NEXT: sarl $30, %ecx
135 ; X32-NEXT: shll $2, %eax
136 ; X32-NEXT: vmovd %eax, %xmm0
137 ; X32-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
138 ; X32-NEXT: vpsrlq $3, %xmm0, %xmm0
139 ; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
140 ; X32-NEXT: vmovss %xmm0, (%esp)
141 ; X32-NEXT: flds (%esp)
142 ; X32-NEXT: popl %eax
143 ; X32-NEXT: retl
144 ;
145 ; X64-LABEL: signbits_ashr_insert_ashr_extract_sitofp:
146 ; X64: # %bb.0:
147 ; X64-NEXT: sarq $30, %rdi
148 ; X64-NEXT: vmovq %rdi, %xmm0
149 ; X64-NEXT: vpsrlq $3, %xmm0, %xmm0
150 ; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
151 ; X64-NEXT: retq
152 %1 = ashr i64 %a0, 30
153 %2 = insertelement <2 x i64> undef, i64 %1, i32 0
154 %3 = insertelement <2 x i64> %2, i64 %a1, i32 1
155 %4 = ashr <2 x i64> %3, <i64 3, i64 3>
156 %5 = extractelement <2 x i64> %4, i32 0
157 %6 = sitofp i64 %5 to float
158 ret float %6
159 }
161 define <4 x double> @signbits_sext_shuffle_sitofp(<4 x i32> %a0, <4 x i64> %a1) nounwind {
162 ; X32-LABEL: signbits_sext_shuffle_sitofp:
163 ; X32: # %bb.0:
164 ; X32-NEXT: vpmovsxdq %xmm0, %xmm1
165 ; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
166 ; X32-NEXT: vpmovsxdq %xmm0, %xmm0
167 ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
168 ; X32-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,0,3,2]
169 ; X32-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1]
170 ; X32-NEXT: vextractf128 $1, %ymm0, %xmm1
171 ; X32-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
172 ; X32-NEXT: vcvtdq2pd %xmm0, %ymm0
173 ; X32-NEXT: retl
174 ;
175 ; X64-LABEL: signbits_sext_shuffle_sitofp:
176 ; X64: # %bb.0:
177 ; X64-NEXT: vpmovsxdq %xmm0, %xmm1
178 ; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
179 ; X64-NEXT: vpmovsxdq %xmm0, %xmm0
180 ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
181 ; X64-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,0,3,2]
182 ; X64-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1]
183 ; X64-NEXT: vextractf128 $1, %ymm0, %xmm1
184 ; X64-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
185 ; X64-NEXT: vcvtdq2pd %xmm0, %ymm0
186 ; X64-NEXT: retq
187 %1 = sext <4 x i32> %a0 to <4 x i64>
188 %2 = shufflevector <4 x i64> %1, <4 x i64>%a1, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
189 %3 = sitofp <4 x i64> %2 to <4 x double>
190 ret <4 x double> %3
191 }
193 ; TODO: Fix vpshufd+vpsrlq -> vpshufd/vpermilps
194 define <2 x double> @signbits_ashr_concat_ashr_extract_sitofp(<2 x i64> %a0, <4 x i64> %a1) nounwind {
195 ; X32-LABEL: signbits_ashr_concat_ashr_extract_sitofp:
196 ; X32: # %bb.0:
197 ; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,3,2,3]
198 ; X32-NEXT: vcvtdq2pd %xmm0, %xmm0
199 ; X32-NEXT: retl
200 ;
201 ; X64-LABEL: signbits_ashr_concat_ashr_extract_sitofp:
202 ; X64: # %bb.0:
203 ; X64-NEXT: vpsrlq $32, %xmm0, %xmm0
204 ; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
205 ; X64-NEXT: vcvtdq2pd %xmm0, %xmm0
206 ; X64-NEXT: retq
207 %1 = ashr <2 x i64> %a0, <i64 16, i64 16>
208 %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
209 %3 = shufflevector <4 x i64> %a1, <4 x i64> %2, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
210 %4 = ashr <4 x i64> %3, <i64 16, i64 16, i64 16, i64 16>
211 %5 = shufflevector <4 x i64> %4, <4 x i64> undef, <2 x i32> <i32 2, i32 3>
212 %6 = sitofp <2 x i64> %5 to <2 x double>
213 ret <2 x double> %6
214 }
216 define float @signbits_ashr_sext_sextinreg_and_extract_sitofp(<2 x i64> %a0, <2 x i64> %a1, i32 %a2) nounwind {
217 ; X32-LABEL: signbits_ashr_sext_sextinreg_and_extract_sitofp:
218 ; X32: # %bb.0:
219 ; X32-NEXT: pushl %eax
220 ; X32-NEXT: vpsrad $29, %xmm0, %xmm0
221 ; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
222 ; X32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
223 ; X32-NEXT: vpand %xmm1, %xmm0, %xmm0
224 ; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
225 ; X32-NEXT: vmovss %xmm0, (%esp)
226 ; X32-NEXT: flds (%esp)
227 ; X32-NEXT: popl %eax
228 ; X32-NEXT: retl
229 ;
230 ; X64-LABEL: signbits_ashr_sext_sextinreg_and_extract_sitofp:
231 ; X64: # %bb.0:
232 ; X64-NEXT: vpsrad $29, %xmm0, %xmm0
233 ; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
234 ; X64-NEXT: vmovd %edi, %xmm1
235 ; X64-NEXT: vpand %xmm1, %xmm0, %xmm0
236 ; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
237 ; X64-NEXT: retq
238 %1 = ashr <2 x i64> %a0, <i64 61, i64 60>
239 %2 = sext i32 %a2 to i64
240 %3 = insertelement <2 x i64> %a1, i64 %2, i32 0
241 %4 = shl <2 x i64> %3, <i64 20, i64 20>
242 %5 = ashr <2 x i64> %4, <i64 20, i64 20>
243 %6 = and <2 x i64> %1, %5
244 %7 = extractelement <2 x i64> %6, i32 0
245 %8 = sitofp i64 %7 to float
246 ret float %8
247 }
249 define float @signbits_ashr_sextvecinreg_bitops_extract_sitofp(<2 x i64> %a0, <4 x i32> %a1) nounwind {
250 ; X32-LABEL: signbits_ashr_sextvecinreg_bitops_extract_sitofp:
251 ; X32: # %bb.0:
252 ; X32-NEXT: pushl %eax
253 ; X32-NEXT: vpsrlq $60, %xmm0, %xmm2
254 ; X32-NEXT: vpsrlq $61, %xmm0, %xmm0
255 ; X32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
256 ; X32-NEXT: vmovdqa {{.*#+}} xmm2 = [4,0,8,0]
257 ; X32-NEXT: vpxor %xmm2, %xmm0, %xmm0
258 ; X32-NEXT: vpsubq %xmm2, %xmm0, %xmm0
259 ; X32-NEXT: vpmovsxdq %xmm1, %xmm1
260 ; X32-NEXT: vpand %xmm1, %xmm0, %xmm2
261 ; X32-NEXT: vpor %xmm1, %xmm2, %xmm1
262 ; X32-NEXT: vpxor %xmm0, %xmm1, %xmm0
263 ; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
264 ; X32-NEXT: vmovss %xmm0, (%esp)
265 ; X32-NEXT: flds (%esp)
266 ; X32-NEXT: popl %eax
267 ; X32-NEXT: retl
268 ;
269 ; X64-LABEL: signbits_ashr_sextvecinreg_bitops_extract_sitofp:
270 ; X64: # %bb.0:
271 ; X64-NEXT: vpsrlq $60, %xmm0, %xmm2
272 ; X64-NEXT: vpsrlq $61, %xmm0, %xmm0
273 ; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
274 ; X64-NEXT: vmovdqa {{.*#+}} xmm2 = [4,8]
275 ; X64-NEXT: vpxor %xmm2, %xmm0, %xmm0
276 ; X64-NEXT: vpsubq %xmm2, %xmm0, %xmm0
277 ; X64-NEXT: vpmovsxdq %xmm1, %xmm1
278 ; X64-NEXT: vpand %xmm1, %xmm0, %xmm2
279 ; X64-NEXT: vpor %xmm1, %xmm2, %xmm1
280 ; X64-NEXT: vpxor %xmm0, %xmm1, %xmm0
281 ; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
282 ; X64-NEXT: retq
283 %1 = ashr <2 x i64> %a0, <i64 61, i64 60>
284 %2 = shufflevector <4 x i32> %a1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
285 %3 = sext <2 x i32> %2 to <2 x i64>
286 %4 = and <2 x i64> %1, %3
287 %5 = or <2 x i64> %4, %3
288 %6 = xor <2 x i64> %5, %1
289 %7 = extractelement <2 x i64> %6, i32 0
290 %8 = sitofp i64 %7 to float
291 ret float %8
292 }
294 define <4 x float> @signbits_ashr_sext_select_shuffle_sitofp(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2, <4 x i32> %a3) nounwind {
295 ; X32-LABEL: signbits_ashr_sext_select_shuffle_sitofp:
296 ; X32: # %bb.0:
297 ; X32-NEXT: pushl %ebp
298 ; X32-NEXT: movl %esp, %ebp
299 ; X32-NEXT: andl $-16, %esp
300 ; X32-NEXT: subl $16, %esp
301 ; X32-NEXT: vpmovsxdq 8(%ebp), %xmm3
302 ; X32-NEXT: vpmovsxdq 16(%ebp), %xmm4
303 ; X32-NEXT: vpsrad $31, %xmm2, %xmm5
304 ; X32-NEXT: vpsrad $1, %xmm2, %xmm6
305 ; X32-NEXT: vpshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
306 ; X32-NEXT: vpblendw {{.*#+}} xmm5 = xmm6[0,1],xmm5[2,3],xmm6[4,5],xmm5[6,7]
307 ; X32-NEXT: vextractf128 $1, %ymm2, %xmm2
308 ; X32-NEXT: vpsrad $31, %xmm2, %xmm6
309 ; X32-NEXT: vpsrad $1, %xmm2, %xmm2
310 ; X32-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
311 ; X32-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm6[2,3],xmm2[4,5],xmm6[6,7]
312 ; X32-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm6
313 ; X32-NEXT: vblendvpd %xmm6, %xmm5, %xmm3, %xmm3
314 ; X32-NEXT: vextractf128 $1, %ymm1, %xmm1
315 ; X32-NEXT: vextractf128 $1, %ymm0, %xmm0
316 ; X32-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
317 ; X32-NEXT: vblendvpd %xmm0, %xmm2, %xmm4, %xmm0
318 ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm3, %ymm0
319 ; X32-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
320 ; X32-NEXT: vextractf128 $1, %ymm0, %xmm1
321 ; X32-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
322 ; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
323 ; X32-NEXT: movl %ebp, %esp
324 ; X32-NEXT: popl %ebp
325 ; X32-NEXT: vzeroupper
326 ; X32-NEXT: retl
327 ;
328 ; X64-LABEL: signbits_ashr_sext_select_shuffle_sitofp:
329 ; X64: # %bb.0:
330 ; X64-NEXT: vpsrad $31, %xmm2, %xmm4
331 ; X64-NEXT: vpsrad $1, %xmm2, %xmm5
332 ; X64-NEXT: vpshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
333 ; X64-NEXT: vpblendw {{.*#+}} xmm4 = xmm5[0,1],xmm4[2,3],xmm5[4,5],xmm4[6,7]
334 ; X64-NEXT: vextractf128 $1, %ymm2, %xmm2
335 ; X64-NEXT: vpsrad $31, %xmm2, %xmm5
336 ; X64-NEXT: vpsrad $1, %xmm2, %xmm2
337 ; X64-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
338 ; X64-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm5[2,3],xmm2[4,5],xmm5[6,7]
339 ; X64-NEXT: vpmovsxdq %xmm3, %xmm5
340 ; X64-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[2,3,0,1]
341 ; X64-NEXT: vpmovsxdq %xmm3, %xmm3
342 ; X64-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm6
343 ; X64-NEXT: vblendvpd %xmm6, %xmm4, %xmm5, %xmm4
344 ; X64-NEXT: vextractf128 $1, %ymm1, %xmm1
345 ; X64-NEXT: vextractf128 $1, %ymm0, %xmm0
346 ; X64-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
347 ; X64-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
348 ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm4, %ymm0
349 ; X64-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
350 ; X64-NEXT: vextractf128 $1, %ymm0, %xmm1
351 ; X64-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
352 ; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
353 ; X64-NEXT: vzeroupper
354 ; X64-NEXT: retq
355 %1 = ashr <4 x i64> %a2, <i64 33, i64 63, i64 33, i64 63>
356 %2 = sext <4 x i32> %a3 to <4 x i64>
357 %3 = icmp eq <4 x i64> %a0, %a1
358 %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2
359 %5 = shufflevector <4 x i64> %4, <4 x i64> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
360 %6 = sitofp <4 x i64> %5 to <4 x float>
361 ret <4 x float> %6
362 }
364 ; Make sure we can preserve sign bit information into the second basic block
365 ; so we can avoid having to shift bit 0 into bit 7 for each element due to
366 ; v32i1->v32i8 promotion and the splitting of v32i8 into 2xv16i8. This requires
367 ; ComputeNumSignBits handling for insert_subvector.
368 define void @cross_bb_signbits_insert_subvec(<32 x i8>* %ptr, <32 x i8> %x, <32 x i8> %z) {
369 ; X32-LABEL: cross_bb_signbits_insert_subvec:
370 ; X32: # %bb.0:
371 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
372 ; X32-NEXT: vextractf128 $1, %ymm0, %xmm2
373 ; X32-NEXT: vpxor %xmm3, %xmm3, %xmm3
374 ; X32-NEXT: vpcmpeqb %xmm3, %xmm2, %xmm2
375 ; X32-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm0
376 ; X32-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
377 ; X32-NEXT: vandnps %ymm1, %ymm0, %ymm1
378 ; X32-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0
379 ; X32-NEXT: vorps %ymm1, %ymm0, %ymm0
380 ; X32-NEXT: vmovaps %ymm0, (%eax)
381 ; X32-NEXT: vzeroupper
382 ; X32-NEXT: retl
383 ;
384 ; X64-LABEL: cross_bb_signbits_insert_subvec:
385 ; X64: # %bb.0:
386 ; X64-NEXT: vextractf128 $1, %ymm0, %xmm2
387 ; X64-NEXT: vpxor %xmm3, %xmm3, %xmm3
388 ; X64-NEXT: vpcmpeqb %xmm3, %xmm2, %xmm2
389 ; X64-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm0
390 ; X64-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
391 ; X64-NEXT: vandnps %ymm1, %ymm0, %ymm1
392 ; X64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
393 ; X64-NEXT: vorps %ymm1, %ymm0, %ymm0
394 ; X64-NEXT: vmovaps %ymm0, (%rdi)
395 ; X64-NEXT: vzeroupper
396 ; X64-NEXT: retq
397 %a = icmp eq <32 x i8> %x, zeroinitializer
398 %b = icmp eq <32 x i8> %x, zeroinitializer
399 %c = and <32 x i1> %a, %b
400 br label %block
402 block:
403 %d = select <32 x i1> %c, <32 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <32 x i8> %z
404 store <32 x i8> %d, <32 x i8>* %ptr, align 32
405 br label %exit
407 exit:
408 ret void
409 }