| blob | 388051846123dd2d6ce54fe1047de3ecb252e5c8 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=ALL,X64
3 ; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefixes=ALL,X32
5 ; shift left
7 define i32 @and_signbit_select_shl(i32 %x, i1 %cond, i32* %dst) {
8 ; X64-LABEL: and_signbit_select_shl:
9 ; X64: # %bb.0:
10 ; X64-NEXT: movl %edi, %eax
11 ; X64-NEXT: andl $16711680, %eax # imm = 0xFF0000
12 ; X64-NEXT: testb $1, %sil
13 ; X64-NEXT: cmovel %edi, %eax
14 ; X64-NEXT: shll $8, %eax
15 ; X64-NEXT: movl %eax, (%rdx)
16 ; X64-NEXT: retq
17 ;
18 ; X32-LABEL: and_signbit_select_shl:
19 ; X32: # %bb.0:
20 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
21 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
22 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
23 ; X32-NEXT: je .LBB0_2
24 ; X32-NEXT: # %bb.1:
25 ; X32-NEXT: andl $16711680, %eax # imm = 0xFF0000
26 ; X32-NEXT: .LBB0_2:
27 ; X32-NEXT: shll $8, %eax
28 ; X32-NEXT: movl %eax, (%ecx)
29 ; X32-NEXT: retl
30 %t0 = and i32 %x, 4294901760 ; 0xFFFF0000
31 %t1 = select i1 %cond, i32 %t0, i32 %x
32 %r = shl i32 %t1, 8
33 store i32 %r, i32* %dst
34 ret i32 %r
35 }
36 define i32 @and_nosignbit_select_shl(i32 %x, i1 %cond, i32* %dst) {
37 ; X64-LABEL: and_nosignbit_select_shl:
38 ; X64: # %bb.0:
39 ; X64-NEXT: movl %edi, %eax
40 ; X64-NEXT: andl $16711680, %eax # imm = 0xFF0000
41 ; X64-NEXT: testb $1, %sil
42 ; X64-NEXT: cmovel %edi, %eax
43 ; X64-NEXT: shll $8, %eax
44 ; X64-NEXT: movl %eax, (%rdx)
45 ; X64-NEXT: retq
46 ;
47 ; X32-LABEL: and_nosignbit_select_shl:
48 ; X32: # %bb.0:
49 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
50 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
51 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
52 ; X32-NEXT: je .LBB1_2
53 ; X32-NEXT: # %bb.1:
54 ; X32-NEXT: andl $16711680, %eax # imm = 0xFF0000
55 ; X32-NEXT: .LBB1_2:
56 ; X32-NEXT: shll $8, %eax
57 ; X32-NEXT: movl %eax, (%ecx)
58 ; X32-NEXT: retl
59 %t0 = and i32 %x, 2147418112 ; 0x7FFF0000
60 %t1 = select i1 %cond, i32 %t0, i32 %x
61 %r = shl i32 %t1, 8
62 store i32 %r, i32* %dst
63 ret i32 %r
64 }
66 define i32 @or_signbit_select_shl(i32 %x, i1 %cond, i32* %dst) {
67 ; X64-LABEL: or_signbit_select_shl:
68 ; X64: # %bb.0:
69 ; X64-NEXT: movl %edi, %eax
70 ; X64-NEXT: orl $16711680, %eax # imm = 0xFF0000
71 ; X64-NEXT: testb $1, %sil
72 ; X64-NEXT: cmovel %edi, %eax
73 ; X64-NEXT: shll $8, %eax
74 ; X64-NEXT: movl %eax, (%rdx)
75 ; X64-NEXT: retq
76 ;
77 ; X32-LABEL: or_signbit_select_shl:
78 ; X32: # %bb.0:
79 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
80 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
81 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
82 ; X32-NEXT: je .LBB2_2
83 ; X32-NEXT: # %bb.1:
84 ; X32-NEXT: orl $16711680, %eax # imm = 0xFF0000
85 ; X32-NEXT: .LBB2_2:
86 ; X32-NEXT: shll $8, %eax
87 ; X32-NEXT: movl %eax, (%ecx)
88 ; X32-NEXT: retl
89 %t0 = or i32 %x, 4294901760 ; 0xFFFF0000
90 %t1 = select i1 %cond, i32 %t0, i32 %x
91 %r = shl i32 %t1, 8
92 store i32 %r, i32* %dst
93 ret i32 %r
94 }
95 define i32 @or_nosignbit_select_shl(i32 %x, i1 %cond, i32* %dst) {
96 ; X64-LABEL: or_nosignbit_select_shl:
97 ; X64: # %bb.0:
98 ; X64-NEXT: movl %edi, %eax
99 ; X64-NEXT: orl $16711680, %eax # imm = 0xFF0000
100 ; X64-NEXT: testb $1, %sil
101 ; X64-NEXT: cmovel %edi, %eax
102 ; X64-NEXT: shll $8, %eax
103 ; X64-NEXT: movl %eax, (%rdx)
104 ; X64-NEXT: retq
105 ;
106 ; X32-LABEL: or_nosignbit_select_shl:
107 ; X32: # %bb.0:
108 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
109 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
110 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
111 ; X32-NEXT: je .LBB3_2
112 ; X32-NEXT: # %bb.1:
113 ; X32-NEXT: orl $16711680, %eax # imm = 0xFF0000
114 ; X32-NEXT: .LBB3_2:
115 ; X32-NEXT: shll $8, %eax
116 ; X32-NEXT: movl %eax, (%ecx)
117 ; X32-NEXT: retl
118 %t0 = or i32 %x, 2147418112 ; 0x7FFF0000
119 %t1 = select i1 %cond, i32 %t0, i32 %x
120 %r = shl i32 %t1, 8
121 store i32 %r, i32* %dst
122 ret i32 %r
123 }
125 define i32 @xor_signbit_select_shl(i32 %x, i1 %cond, i32* %dst) {
126 ; X64-LABEL: xor_signbit_select_shl:
127 ; X64: # %bb.0:
128 ; X64-NEXT: movl %edi, %eax
129 ; X64-NEXT: xorl $16711680, %eax # imm = 0xFF0000
130 ; X64-NEXT: testb $1, %sil
131 ; X64-NEXT: cmovel %edi, %eax
132 ; X64-NEXT: shll $8, %eax
133 ; X64-NEXT: movl %eax, (%rdx)
134 ; X64-NEXT: retq
135 ;
136 ; X32-LABEL: xor_signbit_select_shl:
137 ; X32: # %bb.0:
138 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
139 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
140 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
141 ; X32-NEXT: je .LBB4_2
142 ; X32-NEXT: # %bb.1:
143 ; X32-NEXT: xorl $16711680, %eax # imm = 0xFF0000
144 ; X32-NEXT: .LBB4_2:
145 ; X32-NEXT: shll $8, %eax
146 ; X32-NEXT: movl %eax, (%ecx)
147 ; X32-NEXT: retl
148 %t0 = xor i32 %x, 4294901760 ; 0xFFFF0000
149 %t1 = select i1 %cond, i32 %t0, i32 %x
150 %r = shl i32 %t1, 8
151 store i32 %r, i32* %dst
152 ret i32 %r
153 }
154 define i32 @xor_nosignbit_select_shl(i32 %x, i1 %cond, i32* %dst) {
155 ; X64-LABEL: xor_nosignbit_select_shl:
156 ; X64: # %bb.0:
157 ; X64-NEXT: movl %edi, %eax
158 ; X64-NEXT: xorl $16711680, %eax # imm = 0xFF0000
159 ; X64-NEXT: testb $1, %sil
160 ; X64-NEXT: cmovel %edi, %eax
161 ; X64-NEXT: shll $8, %eax
162 ; X64-NEXT: movl %eax, (%rdx)
163 ; X64-NEXT: retq
164 ;
165 ; X32-LABEL: xor_nosignbit_select_shl:
166 ; X32: # %bb.0:
167 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
168 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
169 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
170 ; X32-NEXT: je .LBB5_2
171 ; X32-NEXT: # %bb.1:
172 ; X32-NEXT: xorl $16711680, %eax # imm = 0xFF0000
173 ; X32-NEXT: .LBB5_2:
174 ; X32-NEXT: shll $8, %eax
175 ; X32-NEXT: movl %eax, (%ecx)
176 ; X32-NEXT: retl
177 %t0 = xor i32 %x, 2147418112 ; 0x7FFF0000
178 %t1 = select i1 %cond, i32 %t0, i32 %x
179 %r = shl i32 %t1, 8
180 store i32 %r, i32* %dst
181 ret i32 %r
182 }
184 define i32 @add_signbit_select_shl(i32 %x, i1 %cond, i32* %dst) {
185 ; X64-LABEL: add_signbit_select_shl:
186 ; X64: # %bb.0:
187 ; X64-NEXT: # kill: def $edi killed $edi def $rdi
188 ; X64-NEXT: leal -65536(%rdi), %eax
189 ; X64-NEXT: testb $1, %sil
190 ; X64-NEXT: cmovel %edi, %eax
191 ; X64-NEXT: shll $8, %eax
192 ; X64-NEXT: movl %eax, (%rdx)
193 ; X64-NEXT: retq
194 ;
195 ; X32-LABEL: add_signbit_select_shl:
196 ; X32: # %bb.0:
197 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
198 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
199 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
200 ; X32-NEXT: je .LBB6_2
201 ; X32-NEXT: # %bb.1:
202 ; X32-NEXT: addl $-65536, %eax # imm = 0xFFFF0000
203 ; X32-NEXT: .LBB6_2:
204 ; X32-NEXT: shll $8, %eax
205 ; X32-NEXT: movl %eax, (%ecx)
206 ; X32-NEXT: retl
207 %t0 = add i32 %x, 4294901760 ; 0xFFFF0000
208 %t1 = select i1 %cond, i32 %t0, i32 %x
209 %r = shl i32 %t1, 8
210 store i32 %r, i32* %dst
211 ret i32 %r
212 }
213 define i32 @add_nosignbit_select_shl(i32 %x, i1 %cond, i32* %dst) {
214 ; X64-LABEL: add_nosignbit_select_shl:
215 ; X64: # %bb.0:
216 ; X64-NEXT: # kill: def $edi killed $edi def $rdi
217 ; X64-NEXT: leal 2147418112(%rdi), %eax
218 ; X64-NEXT: testb $1, %sil
219 ; X64-NEXT: cmovel %edi, %eax
220 ; X64-NEXT: shll $8, %eax
221 ; X64-NEXT: movl %eax, (%rdx)
222 ; X64-NEXT: retq
223 ;
224 ; X32-LABEL: add_nosignbit_select_shl:
225 ; X32: # %bb.0:
226 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
227 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
228 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
229 ; X32-NEXT: je .LBB7_2
230 ; X32-NEXT: # %bb.1:
231 ; X32-NEXT: addl $2147418112, %eax # imm = 0x7FFF0000
232 ; X32-NEXT: .LBB7_2:
233 ; X32-NEXT: shll $8, %eax
234 ; X32-NEXT: movl %eax, (%ecx)
235 ; X32-NEXT: retl
236 %t0 = add i32 %x, 2147418112 ; 0x7FFF0000
237 %t1 = select i1 %cond, i32 %t0, i32 %x
238 %r = shl i32 %t1, 8
239 store i32 %r, i32* %dst
240 ret i32 %r
241 }
243 ; logical shift right
245 define i32 @and_signbit_select_lshr(i32 %x, i1 %cond, i32* %dst) {
246 ; X64-LABEL: and_signbit_select_lshr:
247 ; X64: # %bb.0:
248 ; X64-NEXT: movl %edi, %eax
249 ; X64-NEXT: andl $-65536, %eax # imm = 0xFFFF0000
250 ; X64-NEXT: testb $1, %sil
251 ; X64-NEXT: cmovel %edi, %eax
252 ; X64-NEXT: shrl $8, %eax
253 ; X64-NEXT: movl %eax, (%rdx)
254 ; X64-NEXT: retq
255 ;
256 ; X32-LABEL: and_signbit_select_lshr:
257 ; X32: # %bb.0:
258 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
259 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
260 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
261 ; X32-NEXT: je .LBB8_2
262 ; X32-NEXT: # %bb.1:
263 ; X32-NEXT: andl $-65536, %eax # imm = 0xFFFF0000
264 ; X32-NEXT: .LBB8_2:
265 ; X32-NEXT: shrl $8, %eax
266 ; X32-NEXT: movl %eax, (%ecx)
267 ; X32-NEXT: retl
268 %t0 = and i32 %x, 4294901760 ; 0xFFFF0000
269 %t1 = select i1 %cond, i32 %t0, i32 %x
270 %r = lshr i32 %t1, 8
271 store i32 %r, i32* %dst
272 ret i32 %r
273 }
274 define i32 @and_nosignbit_select_lshr(i32 %x, i1 %cond, i32* %dst) {
275 ; X64-LABEL: and_nosignbit_select_lshr:
276 ; X64: # %bb.0:
277 ; X64-NEXT: movl %edi, %eax
278 ; X64-NEXT: andl $2147418112, %eax # imm = 0x7FFF0000
279 ; X64-NEXT: testb $1, %sil
280 ; X64-NEXT: cmovel %edi, %eax
281 ; X64-NEXT: shrl $8, %eax
282 ; X64-NEXT: movl %eax, (%rdx)
283 ; X64-NEXT: retq
284 ;
285 ; X32-LABEL: and_nosignbit_select_lshr:
286 ; X32: # %bb.0:
287 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
288 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
289 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
290 ; X32-NEXT: je .LBB9_2
291 ; X32-NEXT: # %bb.1:
292 ; X32-NEXT: andl $2147418112, %eax # imm = 0x7FFF0000
293 ; X32-NEXT: .LBB9_2:
294 ; X32-NEXT: shrl $8, %eax
295 ; X32-NEXT: movl %eax, (%ecx)
296 ; X32-NEXT: retl
297 %t0 = and i32 %x, 2147418112 ; 0x7FFF0000
298 %t1 = select i1 %cond, i32 %t0, i32 %x
299 %r = lshr i32 %t1, 8
300 store i32 %r, i32* %dst
301 ret i32 %r
302 }
304 define i32 @or_signbit_select_lshr(i32 %x, i1 %cond, i32* %dst) {
305 ; X64-LABEL: or_signbit_select_lshr:
306 ; X64: # %bb.0:
307 ; X64-NEXT: movl %edi, %eax
308 ; X64-NEXT: orl $-65536, %eax # imm = 0xFFFF0000
309 ; X64-NEXT: testb $1, %sil
310 ; X64-NEXT: cmovel %edi, %eax
311 ; X64-NEXT: shrl $8, %eax
312 ; X64-NEXT: movl %eax, (%rdx)
313 ; X64-NEXT: retq
314 ;
315 ; X32-LABEL: or_signbit_select_lshr:
316 ; X32: # %bb.0:
317 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
318 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
319 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
320 ; X32-NEXT: je .LBB10_2
321 ; X32-NEXT: # %bb.1:
322 ; X32-NEXT: orl $-65536, %eax # imm = 0xFFFF0000
323 ; X32-NEXT: .LBB10_2:
324 ; X32-NEXT: shrl $8, %eax
325 ; X32-NEXT: movl %eax, (%ecx)
326 ; X32-NEXT: retl
327 %t0 = or i32 %x, 4294901760 ; 0xFFFF0000
328 %t1 = select i1 %cond, i32 %t0, i32 %x
329 %r = lshr i32 %t1, 8
330 store i32 %r, i32* %dst
331 ret i32 %r
332 }
333 define i32 @or_nosignbit_select_lshr(i32 %x, i1 %cond, i32* %dst) {
334 ; X64-LABEL: or_nosignbit_select_lshr:
335 ; X64: # %bb.0:
336 ; X64-NEXT: movl %edi, %eax
337 ; X64-NEXT: orl $2147418112, %eax # imm = 0x7FFF0000
338 ; X64-NEXT: testb $1, %sil
339 ; X64-NEXT: cmovel %edi, %eax
340 ; X64-NEXT: shrl $8, %eax
341 ; X64-NEXT: movl %eax, (%rdx)
342 ; X64-NEXT: retq
343 ;
344 ; X32-LABEL: or_nosignbit_select_lshr:
345 ; X32: # %bb.0:
346 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
347 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
348 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
349 ; X32-NEXT: je .LBB11_2
350 ; X32-NEXT: # %bb.1:
351 ; X32-NEXT: orl $2147418112, %eax # imm = 0x7FFF0000
352 ; X32-NEXT: .LBB11_2:
353 ; X32-NEXT: shrl $8, %eax
354 ; X32-NEXT: movl %eax, (%ecx)
355 ; X32-NEXT: retl
356 %t0 = or i32 %x, 2147418112 ; 0x7FFF0000
357 %t1 = select i1 %cond, i32 %t0, i32 %x
358 %r = lshr i32 %t1, 8
359 store i32 %r, i32* %dst
360 ret i32 %r
361 }
363 define i32 @xor_signbit_select_lshr(i32 %x, i1 %cond, i32* %dst) {
364 ; X64-LABEL: xor_signbit_select_lshr:
365 ; X64: # %bb.0:
366 ; X64-NEXT: movl %edi, %eax
367 ; X64-NEXT: xorl $-65536, %eax # imm = 0xFFFF0000
368 ; X64-NEXT: testb $1, %sil
369 ; X64-NEXT: cmovel %edi, %eax
370 ; X64-NEXT: shrl $8, %eax
371 ; X64-NEXT: movl %eax, (%rdx)
372 ; X64-NEXT: retq
373 ;
374 ; X32-LABEL: xor_signbit_select_lshr:
375 ; X32: # %bb.0:
376 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
377 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
378 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
379 ; X32-NEXT: je .LBB12_2
380 ; X32-NEXT: # %bb.1:
381 ; X32-NEXT: xorl $-65536, %eax # imm = 0xFFFF0000
382 ; X32-NEXT: .LBB12_2:
383 ; X32-NEXT: shrl $8, %eax
384 ; X32-NEXT: movl %eax, (%ecx)
385 ; X32-NEXT: retl
386 %t0 = xor i32 %x, 4294901760 ; 0xFFFF0000
387 %t1 = select i1 %cond, i32 %t0, i32 %x
388 %r = lshr i32 %t1, 8
389 store i32 %r, i32* %dst
390 ret i32 %r
391 }
392 define i32 @xor_nosignbit_select_lshr(i32 %x, i1 %cond, i32* %dst) {
393 ; X64-LABEL: xor_nosignbit_select_lshr:
394 ; X64: # %bb.0:
395 ; X64-NEXT: movl %edi, %eax
396 ; X64-NEXT: xorl $2147418112, %eax # imm = 0x7FFF0000
397 ; X64-NEXT: testb $1, %sil
398 ; X64-NEXT: cmovel %edi, %eax
399 ; X64-NEXT: shrl $8, %eax
400 ; X64-NEXT: movl %eax, (%rdx)
401 ; X64-NEXT: retq
402 ;
403 ; X32-LABEL: xor_nosignbit_select_lshr:
404 ; X32: # %bb.0:
405 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
406 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
407 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
408 ; X32-NEXT: je .LBB13_2
409 ; X32-NEXT: # %bb.1:
410 ; X32-NEXT: xorl $2147418112, %eax # imm = 0x7FFF0000
411 ; X32-NEXT: .LBB13_2:
412 ; X32-NEXT: shrl $8, %eax
413 ; X32-NEXT: movl %eax, (%ecx)
414 ; X32-NEXT: retl
415 %t0 = xor i32 %x, 2147418112 ; 0x7FFF0000
416 %t1 = select i1 %cond, i32 %t0, i32 %x
417 %r = lshr i32 %t1, 8
418 store i32 %r, i32* %dst
419 ret i32 %r
420 }
422 define i32 @add_signbit_select_lshr(i32 %x, i1 %cond, i32* %dst) {
423 ; X64-LABEL: add_signbit_select_lshr:
424 ; X64: # %bb.0:
425 ; X64-NEXT: # kill: def $edi killed $edi def $rdi
426 ; X64-NEXT: leal -65536(%rdi), %eax
427 ; X64-NEXT: testb $1, %sil
428 ; X64-NEXT: cmovel %edi, %eax
429 ; X64-NEXT: shrl $8, %eax
430 ; X64-NEXT: movl %eax, (%rdx)
431 ; X64-NEXT: retq
432 ;
433 ; X32-LABEL: add_signbit_select_lshr:
434 ; X32: # %bb.0:
435 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
436 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
437 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
438 ; X32-NEXT: je .LBB14_2
439 ; X32-NEXT: # %bb.1:
440 ; X32-NEXT: addl $-65536, %eax # imm = 0xFFFF0000
441 ; X32-NEXT: .LBB14_2:
442 ; X32-NEXT: shrl $8, %eax
443 ; X32-NEXT: movl %eax, (%ecx)
444 ; X32-NEXT: retl
445 %t0 = add i32 %x, 4294901760 ; 0xFFFF0000
446 %t1 = select i1 %cond, i32 %t0, i32 %x
447 %r = lshr i32 %t1, 8
448 store i32 %r, i32* %dst
449 ret i32 %r
450 }
451 define i32 @add_nosignbit_select_lshr(i32 %x, i1 %cond, i32* %dst) {
452 ; X64-LABEL: add_nosignbit_select_lshr:
453 ; X64: # %bb.0:
454 ; X64-NEXT: # kill: def $edi killed $edi def $rdi
455 ; X64-NEXT: leal 2147418112(%rdi), %eax
456 ; X64-NEXT: testb $1, %sil
457 ; X64-NEXT: cmovel %edi, %eax
458 ; X64-NEXT: shrl $8, %eax
459 ; X64-NEXT: movl %eax, (%rdx)
460 ; X64-NEXT: retq
461 ;
462 ; X32-LABEL: add_nosignbit_select_lshr:
463 ; X32: # %bb.0:
464 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
465 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
466 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
467 ; X32-NEXT: je .LBB15_2
468 ; X32-NEXT: # %bb.1:
469 ; X32-NEXT: addl $2147418112, %eax # imm = 0x7FFF0000
470 ; X32-NEXT: .LBB15_2:
471 ; X32-NEXT: shrl $8, %eax
472 ; X32-NEXT: movl %eax, (%ecx)
473 ; X32-NEXT: retl
474 %t0 = add i32 %x, 2147418112 ; 0x7FFF0000
475 %t1 = select i1 %cond, i32 %t0, i32 %x
476 %r = lshr i32 %t1, 8
477 store i32 %r, i32* %dst
478 ret i32 %r
479 }
481 ; arithmetic shift right
483 define i32 @and_signbit_select_ashr(i32 %x, i1 %cond, i32* %dst) {
484 ; X64-LABEL: and_signbit_select_ashr:
485 ; X64: # %bb.0:
486 ; X64-NEXT: movl %edi, %eax
487 ; X64-NEXT: andl $-65536, %eax # imm = 0xFFFF0000
488 ; X64-NEXT: testb $1, %sil
489 ; X64-NEXT: cmovel %edi, %eax
490 ; X64-NEXT: sarl $8, %eax
491 ; X64-NEXT: movl %eax, (%rdx)
492 ; X64-NEXT: retq
493 ;
494 ; X32-LABEL: and_signbit_select_ashr:
495 ; X32: # %bb.0:
496 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
497 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
498 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
499 ; X32-NEXT: je .LBB16_2
500 ; X32-NEXT: # %bb.1:
501 ; X32-NEXT: andl $-65536, %eax # imm = 0xFFFF0000
502 ; X32-NEXT: .LBB16_2:
503 ; X32-NEXT: sarl $8, %eax
504 ; X32-NEXT: movl %eax, (%ecx)
505 ; X32-NEXT: retl
506 %t0 = and i32 %x, 4294901760 ; 0xFFFF0000
507 %t1 = select i1 %cond, i32 %t0, i32 %x
508 %r = ashr i32 %t1, 8
509 store i32 %r, i32* %dst
510 ret i32 %r
511 }
512 define i32 @and_nosignbit_select_ashr(i32 %x, i1 %cond, i32* %dst) {
513 ; X64-LABEL: and_nosignbit_select_ashr:
514 ; X64: # %bb.0:
515 ; X64-NEXT: movl %edi, %eax
516 ; X64-NEXT: andl $2147418112, %eax # imm = 0x7FFF0000
517 ; X64-NEXT: testb $1, %sil
518 ; X64-NEXT: cmovel %edi, %eax
519 ; X64-NEXT: sarl $8, %eax
520 ; X64-NEXT: movl %eax, (%rdx)
521 ; X64-NEXT: retq
522 ;
523 ; X32-LABEL: and_nosignbit_select_ashr:
524 ; X32: # %bb.0:
525 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
526 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
527 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
528 ; X32-NEXT: je .LBB17_2
529 ; X32-NEXT: # %bb.1:
530 ; X32-NEXT: andl $2147418112, %eax # imm = 0x7FFF0000
531 ; X32-NEXT: .LBB17_2:
532 ; X32-NEXT: sarl $8, %eax
533 ; X32-NEXT: movl %eax, (%ecx)
534 ; X32-NEXT: retl
535 %t0 = and i32 %x, 2147418112 ; 0x7FFF0000
536 %t1 = select i1 %cond, i32 %t0, i32 %x
537 %r = ashr i32 %t1, 8
538 store i32 %r, i32* %dst
539 ret i32 %r
540 }
542 define i32 @or_signbit_select_ashr(i32 %x, i1 %cond, i32* %dst) {
543 ; X64-LABEL: or_signbit_select_ashr:
544 ; X64: # %bb.0:
545 ; X64-NEXT: movl %edi, %eax
546 ; X64-NEXT: orl $-65536, %eax # imm = 0xFFFF0000
547 ; X64-NEXT: testb $1, %sil
548 ; X64-NEXT: cmovel %edi, %eax
549 ; X64-NEXT: sarl $8, %eax
550 ; X64-NEXT: movl %eax, (%rdx)
551 ; X64-NEXT: retq
552 ;
553 ; X32-LABEL: or_signbit_select_ashr:
554 ; X32: # %bb.0:
555 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
556 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
557 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
558 ; X32-NEXT: je .LBB18_2
559 ; X32-NEXT: # %bb.1:
560 ; X32-NEXT: orl $-65536, %eax # imm = 0xFFFF0000
561 ; X32-NEXT: .LBB18_2:
562 ; X32-NEXT: sarl $8, %eax
563 ; X32-NEXT: movl %eax, (%ecx)
564 ; X32-NEXT: retl
565 %t0 = or i32 %x, 4294901760 ; 0xFFFF0000
566 %t1 = select i1 %cond, i32 %t0, i32 %x
567 %r = ashr i32 %t1, 8
568 store i32 %r, i32* %dst
569 ret i32 %r
570 }
571 define i32 @or_nosignbit_select_ashr(i32 %x, i1 %cond, i32* %dst) {
572 ; X64-LABEL: or_nosignbit_select_ashr:
573 ; X64: # %bb.0:
574 ; X64-NEXT: movl %edi, %eax
575 ; X64-NEXT: orl $2147418112, %eax # imm = 0x7FFF0000
576 ; X64-NEXT: testb $1, %sil
577 ; X64-NEXT: cmovel %edi, %eax
578 ; X64-NEXT: sarl $8, %eax
579 ; X64-NEXT: movl %eax, (%rdx)
580 ; X64-NEXT: retq
581 ;
582 ; X32-LABEL: or_nosignbit_select_ashr:
583 ; X32: # %bb.0:
584 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
585 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
586 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
587 ; X32-NEXT: je .LBB19_2
588 ; X32-NEXT: # %bb.1:
589 ; X32-NEXT: orl $2147418112, %eax # imm = 0x7FFF0000
590 ; X32-NEXT: .LBB19_2:
591 ; X32-NEXT: sarl $8, %eax
592 ; X32-NEXT: movl %eax, (%ecx)
593 ; X32-NEXT: retl
594 %t0 = or i32 %x, 2147418112 ; 0x7FFF0000
595 %t1 = select i1 %cond, i32 %t0, i32 %x
596 %r = ashr i32 %t1, 8
597 store i32 %r, i32* %dst
598 ret i32 %r
599 }
601 define i32 @xor_signbit_select_ashr(i32 %x, i1 %cond, i32* %dst) {
602 ; X64-LABEL: xor_signbit_select_ashr:
603 ; X64: # %bb.0:
604 ; X64-NEXT: movl %edi, %eax
605 ; X64-NEXT: xorl $-65536, %eax # imm = 0xFFFF0000
606 ; X64-NEXT: testb $1, %sil
607 ; X64-NEXT: cmovel %edi, %eax
608 ; X64-NEXT: sarl $8, %eax
609 ; X64-NEXT: movl %eax, (%rdx)
610 ; X64-NEXT: retq
611 ;
612 ; X32-LABEL: xor_signbit_select_ashr:
613 ; X32: # %bb.0:
614 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
615 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
616 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
617 ; X32-NEXT: je .LBB20_2
618 ; X32-NEXT: # %bb.1:
619 ; X32-NEXT: xorl $-65536, %eax # imm = 0xFFFF0000
620 ; X32-NEXT: .LBB20_2:
621 ; X32-NEXT: sarl $8, %eax
622 ; X32-NEXT: movl %eax, (%ecx)
623 ; X32-NEXT: retl
624 %t0 = xor i32 %x, 4294901760 ; 0xFFFF0000
625 %t1 = select i1 %cond, i32 %t0, i32 %x
626 %r = ashr i32 %t1, 8
627 store i32 %r, i32* %dst
628 ret i32 %r
629 }
630 define i32 @xor_nosignbit_select_ashr(i32 %x, i1 %cond, i32* %dst) {
631 ; X64-LABEL: xor_nosignbit_select_ashr:
632 ; X64: # %bb.0:
633 ; X64-NEXT: movl %edi, %eax
634 ; X64-NEXT: xorl $2147418112, %eax # imm = 0x7FFF0000
635 ; X64-NEXT: testb $1, %sil
636 ; X64-NEXT: cmovel %edi, %eax
637 ; X64-NEXT: sarl $8, %eax
638 ; X64-NEXT: movl %eax, (%rdx)
639 ; X64-NEXT: retq
640 ;
641 ; X32-LABEL: xor_nosignbit_select_ashr:
642 ; X32: # %bb.0:
643 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
644 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
645 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
646 ; X32-NEXT: je .LBB21_2
647 ; X32-NEXT: # %bb.1:
648 ; X32-NEXT: xorl $2147418112, %eax # imm = 0x7FFF0000
649 ; X32-NEXT: .LBB21_2:
650 ; X32-NEXT: sarl $8, %eax
651 ; X32-NEXT: movl %eax, (%ecx)
652 ; X32-NEXT: retl
653 %t0 = xor i32 %x, 2147418112 ; 0x7FFF0000
654 %t1 = select i1 %cond, i32 %t0, i32 %x
655 %r = ashr i32 %t1, 8
656 store i32 %r, i32* %dst
657 ret i32 %r
658 }
660 define i32 @add_signbit_select_ashr(i32 %x, i1 %cond, i32* %dst) {
661 ; X64-LABEL: add_signbit_select_ashr:
662 ; X64: # %bb.0:
663 ; X64-NEXT: # kill: def $edi killed $edi def $rdi
664 ; X64-NEXT: leal -65536(%rdi), %eax
665 ; X64-NEXT: testb $1, %sil
666 ; X64-NEXT: cmovel %edi, %eax
667 ; X64-NEXT: sarl $8, %eax
668 ; X64-NEXT: movl %eax, (%rdx)
669 ; X64-NEXT: retq
670 ;
671 ; X32-LABEL: add_signbit_select_ashr:
672 ; X32: # %bb.0:
673 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
674 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
675 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
676 ; X32-NEXT: je .LBB22_2
677 ; X32-NEXT: # %bb.1:
678 ; X32-NEXT: addl $-65536, %eax # imm = 0xFFFF0000
679 ; X32-NEXT: .LBB22_2:
680 ; X32-NEXT: sarl $8, %eax
681 ; X32-NEXT: movl %eax, (%ecx)
682 ; X32-NEXT: retl
683 %t0 = add i32 %x, 4294901760 ; 0xFFFF0000
684 %t1 = select i1 %cond, i32 %t0, i32 %x
685 %r = ashr i32 %t1, 8
686 store i32 %r, i32* %dst
687 ret i32 %r
688 }
689 define i32 @add_nosignbit_select_ashr(i32 %x, i1 %cond, i32* %dst) {
690 ; X64-LABEL: add_nosignbit_select_ashr:
691 ; X64: # %bb.0:
692 ; X64-NEXT: # kill: def $edi killed $edi def $rdi
693 ; X64-NEXT: leal 2147418112(%rdi), %eax
694 ; X64-NEXT: testb $1, %sil
695 ; X64-NEXT: cmovel %edi, %eax
696 ; X64-NEXT: sarl $8, %eax
697 ; X64-NEXT: movl %eax, (%rdx)
698 ; X64-NEXT: retq
699 ;
700 ; X32-LABEL: add_nosignbit_select_ashr:
701 ; X32: # %bb.0:
702 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
703 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
704 ; X32-NEXT: testb $1, {{[0-9]+}}(%esp)
705 ; X32-NEXT: je .LBB23_2
706 ; X32-NEXT: # %bb.1:
707 ; X32-NEXT: addl $2147418112, %eax # imm = 0x7FFF0000
708 ; X32-NEXT: .LBB23_2:
709 ; X32-NEXT: sarl $8, %eax
710 ; X32-NEXT: movl %eax, (%ecx)
711 ; X32-NEXT: retl
712 %t0 = add i32 %x, 2147418112 ; 0x7FFF0000
713 %t1 = select i1 %cond, i32 %t0, i32 %x
714 %r = ashr i32 %t1, 8
715 store i32 %r, i32* %dst
716 ret i32 %r
717 }