[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / SVE / adr-diagnostics.s
blob2bab1f7faeaa11fd50f2e6637146b66cfd4b96b2
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
3 // --------------------------------------------------------------------------//
4 // Invalid addressing modes.
6 adr z0.s, [z0.s, z0.d]
7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
8 // CHECK-NEXT: adr z0.s, [z0.s, z0.d]
9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
11 adr z0.s, [z0.s, z0.s, lsl]
12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier
13 // CHECK-NEXT: adr z0.s, [z0.s, z0.s, lsl]
14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
16 adr z0.s, [z0.s, z0.s, lsl #4]
17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s'
18 // CHECK-NEXT: adr z0.s, [z0.s, z0.s, lsl #4]
19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
21 adr z0.s, [z0.s, z0.s, uxtw]
22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s'
23 // CHECK-NEXT: adr z0.s, [z0.s, z0.s, uxtw]
24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
26 adr z0.s, [z0.s, z0.s, sxtw]
27 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s'
28 // CHECK-NEXT: adr z0.s, [z0.s, z0.s, sxtw]
29 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
31 adr z0.d, [z0.d, z0.s]
32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
33 // CHECK-NEXT: adr z0.d, [z0.d, z0.s]
34 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
36 adr z0.d, [z0.d, z0.s, uxtw]
37 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
38 // CHECK-NEXT: adr z0.d, [z0.d, z0.s, uxtw]
39 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
41 adr z0.d, [z0.d, z0.s, sxtw]
42 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
43 // CHECK-NEXT: adr z0.d, [z0.d, z0.s, sxtw]
44 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
46 adr z0.d, [z0.d, z0.d, lsl #4]
47 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
48 // CHECK-NEXT: adr z0.d, [z0.d, z0.d, lsl #4]
49 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
51 adr z0.d, [z0.d, z0.d, uxtw #4]
52 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
53 // CHECK-NEXT: adr z0.d, [z0.d, z0.d, uxtw #4]
54 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
56 adr z0.d, [z0.d, z0.d, sxtw #4]
57 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
58 // CHECK-NEXT: adr z0.d, [z0.d, z0.d, sxtw #4]
59 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
62 // --------------------------------------------------------------------------//
63 // Negative tests for instructions that are incompatible with movprfx
65 movprfx z0.d, p0/z, z7.d
66 adr z0.d, [z0.d, z0.d, sxtw #3]
67 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
68 // CHECK-NEXT: adr z0.d, [z0.d, z0.d, sxtw #3]
69 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
71 movprfx z0, z7
72 adr z0.d, [z0.d, z0.d, sxtw #3]
73 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
74 // CHECK-NEXT: adr z0.d, [z0.d, z0.d, sxtw #3]
75 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: