test/MC/AArch64/SVE/faclt-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
   2
   3 faclt   p0.b, p0/z, z0.b, z0.b
   4 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
   5 // CHECK-NEXT: faclt   p0.b, p0/z, z0.b, z0.b
   6 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
   7
   8 faclt   p0.b, p0/z, z0.b, #0.0
   9 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected floating point literal
  10 // CHECK-NEXT: faclt   p0.b, p0/z, z0.b, #0.0
  11 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  12
  13
  14 // --------------------------------------------------------------------------//
  15 // Negative tests for instructions that are incompatible with movprfx
  16
  17 movprfx z0.d, p0/z, z7.d
  18 faclt   p0.d, p0/z, z0.d, z1.d
  19 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
  20 // CHECK-NEXT: faclt   p0.d, p0/z, z0.d, z1.d
  21 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  22
  23 movprfx z0, z7
  24 faclt   p0.d, p0/z, z0.d, z1.d
  25 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
  26 // CHECK-NEXT: faclt   p0.d, p0/z, z0.d, z1.d
  27 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: