[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / SVE / fcvtzu-diagnostics.s
blob413e99285cf8fa79fda66e268967a78202bbd1e3
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
3 fcvtzu z0.h, p0/m, z0.s
4 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
5 // CHECK-NEXT: fcvtzu z0.h, p0/m, z0.s
6 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
8 fcvtzu z0.h, p0/m, z0.d
9 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
10 // CHECK-NEXT: fcvtzu z0.h, p0/m, z0.d
11 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
14 // --------------------------------------------------------------------------//
15 // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
17 fcvtzu z0.h, p8/m, z0.h
18 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
19 // CHECK-NEXT: fcvtzu z0.h, p8/m, z0.h
20 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: