[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / SVE / fnmls-diagnostics.s
blob36b6214a0118bb6df9bf641e6da68051c47cb1c8
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
4 // ------------------------------------------------------------------------- //
5 // Invalid predicate
7 fnmls z0.h, p8/m, z1.h, z2.h
8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
9 // CHECK-NEXT: fnmls z0.h, p8/m, z1.h, z2.h
10 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
13 // ------------------------------------------------------------------------- //
14 // Invalid element width
16 fnmls z0.s, p7/m, z1.h, z2.h
17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
18 // CHECK-NEXT: fnmls z0.s, p7/m, z1.h, z2.h
19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
22 // ------------------------------------------------------------------------- //
23 // Element index is not allowed
25 fnmls z0.h, p7/m, z1.h, z2.h[0]
26 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
27 // CHECK-NEXT: fnmls z0.h, p7/m, z1.h, z2.h[0]
28 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: