[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / SVE / frintn-diagnostics.s
blobf5fb0705243643f992fc2d53c4008f8fd3e54ca0
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
3 frintn z0.b, p0/m, z0.b
4 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
5 // CHECK-NEXT: frintn z0.b, p0/m, z0.b
6 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
8 frintn z0.s, p0/z, z0.s
9 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
10 // CHECK-NEXT: frintn z0.s, p0/z, z0.s
11 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
13 frintn z0.s, p8/m, z0.s
14 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
15 // CHECK-NEXT: frintn z0.s, p8/m, z0.s
16 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: