[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / SVE / ftssel-diagnostics.s
blobc0cfac0613112494356a5800e78e7f955205ea8c
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
3 ftssel z0.b, z1.b, z31.b
4 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
5 // CHECK-NEXT: ftssel z0.b, z1.b, z31.b
6 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
8 // --------------------------------------------------------------------------//
9 // Negative tests for instructions that are incompatible with movprfx
11 movprfx z0.d, p0/z, z7.d
12 ftssel z0.d, z1.d, z31.d
13 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
14 // CHECK-NEXT: ftssel z0.d, z1.d, z31.d
15 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
17 movprfx z0, z7
18 ftssel z0.d, z1.d, z31.d
19 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
20 // CHECK-NEXT: ftssel z0.d, z1.d, z31.d
21 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: