[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / SVE / ld1rsb-diagnostics.s
blob5da5dee3e2a66a78320ea23aa3a4fc6c2c74061d
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
3 // --------------------------------------------------------------------------//
4 // Invalid immediate (in range [0, 63]).
6 ld1rsb z0.h, p1/z, [x0, #-1]
7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be in range [0, 63].
8 // CHECK-NEXT: ld1rsb z0.h, p1/z, [x0, #-1]
9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
11 ld1rsb z0.h, p1/z, [x0, #64]
12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be in range [0, 63].
13 // CHECK-NEXT: ld1rsb z0.h, p1/z, [x0, #64]
14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
17 // --------------------------------------------------------------------------//
18 // Invalid result vector element size
20 ld1rsb z0.b, p1/z, [x0]
21 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
22 // CHECK-NEXT: ld1rsb z0.b, p1/z, [x0]
23 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
26 // --------------------------------------------------------------------------//
27 // restricted predicate has range [0, 7].
29 ld1rsb z0.h, p8/z, [x0]
30 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
31 // CHECK-NEXT: ld1rsb z0.h, p8/z, [x0]
32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
35 // --------------------------------------------------------------------------//
36 // Negative tests for instructions that are incompatible with movprfx
38 movprfx z31.d, p7/z, z6.d
39 ld1rsb { z31.d }, p7/z, [sp, #63]
40 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
41 // CHECK-NEXT: ld1rsb { z31.d }, p7/z, [sp, #63]
42 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
44 movprfx z31, z6
45 ld1rsb { z31.d }, p7/z, [sp, #63]
46 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
47 // CHECK-NEXT: ld1rsb { z31.d }, p7/z, [sp, #63]
48 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: