[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / SVE / ldff1b-diagnostics.s
blobdf4091b1a438b7d87e4b80082980189e6c717dc0
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
3 // --------------------------------------------------------------------------//
4 // restricted predicate has range [0, 7].
6 ldff1b z27.b, p8/z, [x0]
7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
8 // CHECK-NEXT: ldff1b z27.b, p8/z, [x0]
9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
11 ldff1b z9.h, p8/z, [x0]
12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
13 // CHECK-NEXT: ldff1b z9.h, p8/z, [x0]
14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
16 ldff1b z12.s, p8/z, [x0]
17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
18 // CHECK-NEXT: ldff1b z12.s, p8/z, [x0]
19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
21 ldff1b z4.d, p8/z, [x0]
22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
23 // CHECK-NEXT: ldff1b z4.d, p8/z, [x0]
24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
26 // --------------------------------------------------------------------------//
27 // Invalid scalar + scalar addressing modes
29 ldff1b z0.b, p0/z, [x0, sp]
30 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
31 // CHECK-NEXT: ldff1b z0.b, p0/z, [x0, sp]
32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
34 ldff1b z0.b, p0/z, [x0, x0, lsl #1]
35 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
36 // CHECK-NEXT: ldff1b z0.b, p0/z, [x0, x0, lsl #1]
37 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
39 ldff1b z0.b, p0/z, [x0, w0]
40 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
41 // CHECK-NEXT: ldff1b z0.b, p0/z, [x0, w0]
42 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
44 ldff1b z0.b, p0/z, [x0, w0, uxtw]
45 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift
46 // CHECK-NEXT: ldff1b z0.b, p0/z, [x0, w0, uxtw]
47 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
49 // --------------------------------------------------------------------------//
50 // Invalid scalar + vector addressing modes
52 ldff1b z0.d, p0/z, [x0, z0.b]
53 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
54 // CHECK-NEXT: ldff1b z0.d, p0/z, [x0, z0.b]
55 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
57 ldff1b z0.d, p0/z, [x0, z0.h]
58 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
59 // CHECK-NEXT: ldff1b z0.d, p0/z, [x0, z0.h]
60 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
62 ldff1b z0.d, p0/z, [x0, z0.s]
63 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
64 // CHECK-NEXT: ldff1b z0.d, p0/z, [x0, z0.s]
65 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
67 ldff1b z0.s, p0/z, [x0, z0.s]
68 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
69 // CHECK-NEXT: ldff1b z0.s, p0/z, [x0, z0.s]
70 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
72 ldff1b z0.s, p0/z, [x0, z0.s, uxtw #1]
73 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
74 // CHECK-NEXT: ldff1b z0.s, p0/z, [x0, z0.s, uxtw #1]
75 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
77 ldff1b z0.s, p0/z, [x0, z0.s, lsl #0]
78 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
79 // CHECK-NEXT: ldff1b z0.s, p0/z, [x0, z0.s, lsl #0]
80 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
82 ldff1b z0.d, p0/z, [x0, z0.d, lsl #1]
83 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
84 // CHECK-NEXT: ldff1b z0.d, p0/z, [x0, z0.d, lsl #1]
85 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
87 ldff1b z0.d, p0/z, [x0, z0.d, sxtw #1]
88 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
89 // CHECK-NEXT: ldff1b z0.d, p0/z, [x0, z0.d, sxtw #1]
90 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
93 // --------------------------------------------------------------------------//
94 // Invalid vector + immediate addressing modes
96 ldff1b z0.s, p0/z, [z0.s, #-1]
97 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
98 // CHECK-NEXT: ldff1b z0.s, p0/z, [z0.s, #-1]
99 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
101 ldff1b z0.s, p0/z, [z0.s, #32]
102 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
103 // CHECK-NEXT: ldff1b z0.s, p0/z, [z0.s, #32]
104 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
106 ldff1b z0.d, p0/z, [z0.d, #-1]
107 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
108 // CHECK-NEXT: ldff1b z0.d, p0/z, [z0.d, #-1]
109 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
111 ldff1b z0.d, p0/z, [z0.d, #32]
112 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
113 // CHECK-NEXT: ldff1b z0.d, p0/z, [z0.d, #32]
114 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
117 // --------------------------------------------------------------------------//
118 // Negative tests for instructions that are incompatible with movprfx
120 movprfx z0.d, p0/z, z7.d
121 ldff1b { z0.d }, p0/z, [z0.d]
122 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
123 // CHECK-NEXT: ldff1b { z0.d }, p0/z, [z0.d]
124 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
126 movprfx z0, z7
127 ldff1b { z0.d }, p0/z, [z0.d]
128 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
129 // CHECK-NEXT: ldff1b { z0.d }, p0/z, [z0.d]
130 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: