[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / SVE / revh-diagnostics.s
blob082e50beaf8643c45717cec0b35f0d41699aef7e
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
4 // ------------------------------------------------------------------------- //
5 // Invalid predicate
7 revh z0.d, p8/m, z0.d
8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
9 // CHECK-NEXT: revh z0.d, p8/m, z0.d
10 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
13 // ------------------------------------------------------------------------- //
14 // Invalid element size
16 revh z0.b, p0/m, z0.b
17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
18 // CHECK-NEXT: revh z0.b, p0/m, z0.b
19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
21 revh z0.h, p0/m, z0.h
22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
23 // CHECK-NEXT: revh z0.h, p0/m, z0.h
24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: