[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / SVE / sxth-diagnostics.s
blob7a48bbde3f4282df39c7a0c0e4c9028ab03e3c06
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
3 // Element size specifiers should match.
4 sxth z0.d, p0/m, z0.s
5 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
6 // CHECK-NEXT: sxth z0.d, p0/m, z0.s
7 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
9 // Missing predicate suffix
10 sxth z29.d, p7, z29.d
11 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
12 // CHECK-NEXT: sxth z29.d, p7, z29.d
13 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
16 // --------------------------------------------------------------------------//
17 // Unsupported element widths
19 sxth z0.b, p0/m, z0.b
20 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
21 // CHECK-NEXT: sxth z0.b, p0/m, z0.b
22 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
24 sxth z0.h, p0/m, z0.h
25 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
26 // CHECK-NEXT: sxth z0.h, p0/m, z0.h
27 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
30 // --------------------------------------------------------------------------//
31 // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
33 sxth z0.s, p8/m, z0.s
34 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
35 // CHECK-NEXT: sxth z0.s, p8/m, z0.s
36 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
38 sxth z0.d, p8/m, z0.d
39 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
40 // CHECK-NEXT: sxth z0.d, p8/m, z0.d
41 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: