[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / SVE2 / adclb-diagnostics.s
blobe2077dea9d591ceba2da3e00479edc5f95015203
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
4 // ------------------------------------------------------------------------- //
5 // Invalid element width
7 adclb z0.b, z1.b, z2.b
8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
9 // CHECK-NEXT: adclb z0.b, z1.b, z2.b
10 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
12 adclb z0.h, z1.h, z2.h
13 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
14 // CHECK-NEXT: adclb z0.h, z1.h, z2.h
15 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18 // --------------------------------------------------------------------------//
19 // Negative tests for instructions that are incompatible with movprfx
21 movprfx z0.d, p0/z, z7.d
22 adclb z0.d, z1.d, z7.d
23 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
24 // CHECK-NEXT: adclb z0.d, z1.d, z7.d
25 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: