test/MC/AArch64/SVE2/tbl-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
   2
   3 tbl z0.b, { z1.b, z2.b }, z3.h
   4 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
   5 // CHECK-NEXT: tbl z0.b, { z1.b, z2.b }, z3.h
   6 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
   7
   8
   9 // --------------------------------------------------------------------------//
  10 // Invalid vector list.
  11
  12 tbl z0.d, { }, z1.d
  13 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
  14 // CHECK-NEXT: tbl z0.d, { }, z1.d
  15 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  16
  17 tbl z0.d, { z1.d, z2.d, z3.d }, z4.d
  18 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  19 // CHECK-NEXT: tbl z0.d, { z1.d, z2.d, z3.d }, z4.d
  20 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  21
  22 tbl z0.d, { z1.d, z2.b }, z3.d
  23 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
  24 // CHECK-NEXT: tbl z0.d, { z1.d, z2.b }, z3.d
  25 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  26
  27 tbl z0.d, { z1.d, z21.d }, z3.d
  28 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
  29 // CHECK-NEXT: tbl z0.d, { z1.d, z21.d }, z3.d
  30 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  31
  32 tbl z0.d, { v0.2d, v1.2d }, z1.d
  33 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  34 // CHECK-NEXT: tbl z0.d, { v0.2d, v1.2d }, z1.d
  35 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  36
  37
  38 // --------------------------------------------------------------------------//
  39 // Negative tests for instructions that are incompatible with movprfx
  40
  41 movprfx z31.d, p0/z, z6.d
  42 tbl  z31.d, { z30.d, z31.d }, z31.d
  43 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
  44 // CHECK-NEXT: tbl  z31.d, { z30.d, z31.d }, z31.d
  45 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  46
  47 movprfx z31, z6
  48 tbl  z31.d, { z30.d, z31.d }, z31.d
  49 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
  50 // CHECK-NEXT: tbl  z31.d, { z30.d, z31.d }, z31.d
  51 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: