[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / SVE2 / urshr-diagnostics.s
blob203d153d671d80bba47369ab661db1c85acb02b4
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
3 urshr z18.b, p0/m, z18.b, #0
4 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
5 // CHECK-NEXT: urshr z18.b, p0/m, z18.b, #0
6 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
8 urshr z1.b, p0/m, z1.b, #9
9 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
10 // CHECK-NEXT: urshr z1.b, p0/m, z1.b, #9
11 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
13 urshr z21.h, p0/m, z21.h, #0
14 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
15 // CHECK-NEXT: urshr z21.h, p0/m, z21.h, #0
16 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18 urshr z14.h, p0/m, z14.h, #17
19 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
20 // CHECK-NEXT: urshr z14.h, p0/m, z14.h, #17
21 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23 urshr z6.s, p0/m, z6.s, #0
24 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
25 // CHECK-NEXT: urshr z6.s, p0/m, z6.s, #0
26 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
28 urshr z23.s, p0/m, z23.s, #33
29 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
30 // CHECK-NEXT: urshr z23.s, p0/m, z23.s, #33
31 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
33 urshr z3.d, p0/m, z3.d, #0
34 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
35 // CHECK-NEXT: urshr z3.d, p0/m, z3.d, #0
36 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
38 urshr z25.d, p0/m, z25.d, #65
39 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
40 // CHECK-NEXT: urshr z25.d, p0/m, z25.d, #65
41 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
44 // --------------------------------------------------------------------------//
45 // Source and Destination Registers must match
47 urshr z0.b, p0/m, z1.b, #1
48 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
49 // CHECK-NEXT: urshr z0.b, p0/m, z1.b, #1
50 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
53 // --------------------------------------------------------------------------//
54 // Element sizes must match
56 urshr z0.b, p0/m, z0.d, #1
57 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
58 // CHECK-NEXT: urshr z0.b, p0/m, z0.d, #1
59 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
61 urshr z0.d, p0/m, z0.b, #1
62 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
63 // CHECK-NEXT: urshr z0.d, p0/m, z0.b, #1
64 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
67 // --------------------------------------------------------------------------//
68 // Invalid predicate
70 urshr z0.b, p0/z, z0.b, #1
71 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
72 // CHECK-NEXT: urshr z0.b, p0/z, z0.b, #1
73 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
75 urshr z0.b, p8/m, z0.b, #1
76 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
77 // CHECK-NEXT: urshr z0.b, p8/m, z0.b, #1
78 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: