[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / SVE2 / whilege-diagnostics.s
blob974deb0597b5e996396755b8e3eef4655191e67c
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
4 // ------------------------------------------------------------------------- //
5 // Invalid scalar registers
7 whilege p15.b, xzr, sp
8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
9 // CHECK-NEXT: whilege p15.b, xzr, sp
10 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
12 whilege p15.b, xzr, w0
13 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
14 // CHECK-NEXT: whilege p15.b, xzr, w0
15 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
17 whilege p15.b, w0, x0
18 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
19 // CHECK-NEXT: whilege p15.b, w0, x0
20 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23 // ------------------------------------------------------------------------- //
24 // Invalid predicate
26 whilege p15, w0, w0
27 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
28 // CHECK-NEXT: whilege p15, w0, w0
29 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: