[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / SVE2 / whilewr-diagnostics.s
blobb2e202985d9171520aab28318794054f17e58b0a
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
4 // ------------------------------------------------------------------------- //
5 // Invalid scalar registers
7 whilewr p15.b, xzr, sp
8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
9 // CHECK-NEXT: whilewr p15.b, xzr, sp
10 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
12 whilewr p15.b, xzr, w0
13 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
14 // CHECK-NEXT: whilewr p15.b, xzr, w0
15 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
17 whilewr p15.b, w0, x0
18 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
19 // CHECK-NEXT: whilewr p15.b, w0, x0
20 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
22 whilewr p15.b, w0, w0
23 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
24 // CHECK-NEXT: whilewr p15.b, w0, w0
25 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: