[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / armv8.5a-specrestrict.s
blob88526b0d6a0c66cf7381c70a31bdc6e89caa1b2c
1 // RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+specrestrict < %s | FileCheck %s
2 // RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s | FileCheck %s
3 // RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-specrestrict < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID
5 mrs x9, ID_PFR2_EL1
7 // CHECK: mrs x9, {{id_pfr2_el1|ID_PFR2_EL1}} // encoding: [0x89,0x03,0x38,0xd5]
8 // NOSPECID: error: expected readable system register
9 // NOSPECID-NEXT: mrs x9, ID_PFR2_EL1
11 mrs x8, SCXTNUM_EL0
12 mrs x7, SCXTNUM_EL1
13 mrs x6, SCXTNUM_EL2
14 mrs x5, SCXTNUM_EL3
15 mrs x4, SCXTNUM_EL12
17 // CHECK: mrs x8, {{scxtnum_el0|SCXTNUM_EL0}} // encoding: [0xe8,0xd0,0x3b,0xd5]
18 // CHECK: mrs x7, {{scxtnum_el1|SCXTNUM_EL1}} // encoding: [0xe7,0xd0,0x38,0xd5]
19 // CHECK: mrs x6, {{scxtnum_el2|SCXTNUM_EL2}} // encoding: [0xe6,0xd0,0x3c,0xd5]
20 // CHECK: mrs x5, {{scxtnum_el3|SCXTNUM_EL3}} // encoding: [0xe5,0xd0,0x3e,0xd5]
21 // CHECK: mrs x4, {{scxtnum_el12|SCXTNUM_EL12}} // encoding: [0xe4,0xd0,0x3d,0xd5]
22 // NOSPECID: error: expected readable system register
23 // NOSPECID-NEXT: mrs x8, {{scxtnum_el0|SCXTNUM_EL0}}
24 // NOSPECID: error: expected readable system register
25 // NOSPECID-NEXT: mrs x7, {{scxtnum_el1|SCXTNUM_EL1}}
26 // NOSPECID: error: expected readable system register
27 // NOSPECID-NEXT: mrs x6, {{scxtnum_el2|SCXTNUM_EL2}}
28 // NOSPECID: error: expected readable system register
29 // NOSPECID-NEXT: mrs x5, {{scxtnum_el3|SCXTNUM_EL3}}
30 // NOSPECID: error: expected readable system register
31 // NOSPECID-NEXT: mrs x4, {{scxtnum_el12|SCXTNUM_EL12}}
33 msr SCXTNUM_EL0, x8
34 msr SCXTNUM_EL1, x7
35 msr SCXTNUM_EL2, x6
36 msr SCXTNUM_EL3, x5
37 msr SCXTNUM_EL12, x4
39 // CHECK: msr {{scxtnum_el0|SCXTNUM_EL0}}, x8 // encoding: [0xe8,0xd0,0x1b,0xd5]
40 // CHECK: msr {{scxtnum_el1|SCXTNUM_EL1}}, x7 // encoding: [0xe7,0xd0,0x18,0xd5]
41 // CHECK: msr {{scxtnum_el2|SCXTNUM_EL2}}, x6 // encoding: [0xe6,0xd0,0x1c,0xd5]
42 // CHECK: msr {{scxtnum_el3|SCXTNUM_EL3}}, x5 // encoding: [0xe5,0xd0,0x1e,0xd5]
43 // CHECK: msr {{scxtnum_el12|SCXTNUM_EL12}}, x4 // encoding: [0xe4,0xd0,0x1d,0xd5]
44 // NOSPECID: error: expected writable system register
45 // NOSPECID-NEXT: {{scxtnum_el0|SCXTNUM_EL0}}
46 // NOSPECID: error: expected writable system register
47 // NOSPECID-NEXT: {{scxtnum_el1|SCXTNUM_EL1}}
48 // NOSPECID: error: expected writable system register
49 // NOSPECID-NEXT: {{scxtnum_el2|SCXTNUM_EL2}}
50 // NOSPECID: error: expected writable system register
51 // NOSPECID-NEXT: {{scxtnum_el3|SCXTNUM_EL3}}
52 // NOSPECID: error: expected writable system register
53 // NOSPECID-NEXT: {{scxtnum_el12|SCXTNUM_EL12}}