[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / directive-cpu-err.s
blob235fbcaa4809cb5f9228fb741c96962099b3b3b6
1 // RUN: not llvm-mc -triple aarch64-linux-gnu %s 2> %t > /dev/null
2 // RUN: FileCheck %s < %t
4 .cpu invalid
5 // CHECK: error: unknown CPU name
7 .cpu generic+wibble+nowobble
8 // CHECK: :[[@LINE-1]]:18: error: unsupported architectural extension
9 // CHECK: :[[@LINE-2]]:25: error: unsupported architectural extension
11 .cpu generic+nofp
12 fminnm d0, d0, d1
13 // CHECK: error: instruction requires: fp-armv8
14 // CHECK-NEXT: fminnm d0, d0, d1
15 // CHECK-NEXT: ^
17 .cpu generic+nosimd
18 addp v0.4s, v0.4s, v0.4s
19 // CHECK: error: instruction requires: neon
20 // CHECK-NEXT: addp v0.4s, v0.4s, v0.4s
21 // CHECK-NEXT: ^
23 .cpu generic+nocrc
24 crc32cx w0, w1, x3
25 // CHECK: error: instruction requires: crc
26 // CHECK-NEXT: crc32cx w0, w1, x3
27 // CHECK-NEXT: ^
29 .cpu generic+nocrypto+crc
30 aesd v0.16b, v2.16b
31 // CHECK: error: instruction requires: aes
32 // CHECK-NEXT: aesd v0.16b, v2.16b
33 // CHECK-NEXT: ^
35 .cpu generic+nolse
36 casa w5, w7, [x20]
37 // CHECK: error: instruction requires: lse
38 // CHECK-NEXT: casa w5, w7, [x20]
39 // CHECK-NEXT: ^
41 .cpu generic+v8.1-a
42 // CHECK: error: unsupported architectural extension
43 // CHECK-NEXT: .cpu generic+v8.1-a
44 // CHECK-NEXT: ^
46 .cpu generic+noaes
47 aese v0.16b, v1.16b
48 // CHECK: error: instruction requires: aes
49 // CHECK-NEXT: aese v0.16b, v1.16b
50 // CHECK-NEXT: ^
52 .cpu generic+nosha2
53 sha1h s0, s1
54 // CHECK: error: instruction requires: sha2
55 // CHECK-NEXT: sha1h s0, s1
56 // CHECK-NEXT: ^
58 .cpu generic+nosha3
59 sha512h q0, q1, v2.2d
60 // CHECK: error: instruction requires: sha3
61 // CHECK-NEXT: sha512h q0, q1, v2.2d
62 // CHECK-NEXT: ^
64 .cpu generic+nosm4
65 sm4e v2.4s, v15.4s
66 // CHECK: error: instruction requires: sm4
67 // CHECK-NEXT: sm4e v2.4s, v15.4s
68 // CHECK-NEXT: ^