[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / neon-rounding-halving-add.s
blob47ac21268020e1cc214745dfa0ab5b6cb44919ed
1 // RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
3 // Check that the assembler can handle the documented syntax for AArch64
6 //------------------------------------------------------------------------------
7 // Vector Integer Rouding Halving Add (Signed)
8 //------------------------------------------------------------------------------
9 srhadd v0.8b, v1.8b, v2.8b
10 srhadd v0.16b, v1.16b, v2.16b
11 srhadd v0.4h, v1.4h, v2.4h
12 srhadd v0.8h, v1.8h, v2.8h
13 srhadd v0.2s, v1.2s, v2.2s
14 srhadd v0.4s, v1.4s, v2.4s
16 // CHECK: srhadd v0.8b, v1.8b, v2.8b // encoding: [0x20,0x14,0x22,0x0e]
17 // CHECK: srhadd v0.16b, v1.16b, v2.16b // encoding: [0x20,0x14,0x22,0x4e]
18 // CHECK: srhadd v0.4h, v1.4h, v2.4h // encoding: [0x20,0x14,0x62,0x0e]
19 // CHECK: srhadd v0.8h, v1.8h, v2.8h // encoding: [0x20,0x14,0x62,0x4e]
20 // CHECK: srhadd v0.2s, v1.2s, v2.2s // encoding: [0x20,0x14,0xa2,0x0e]
21 // CHECK: srhadd v0.4s, v1.4s, v2.4s // encoding: [0x20,0x14,0xa2,0x4e]
23 //------------------------------------------------------------------------------
24 // Vector Integer Rouding Halving Add (Unsigned)
25 //------------------------------------------------------------------------------
26 urhadd v0.8b, v1.8b, v2.8b
27 urhadd v0.16b, v1.16b, v2.16b
28 urhadd v0.4h, v1.4h, v2.4h
29 urhadd v0.8h, v1.8h, v2.8h
30 urhadd v0.2s, v1.2s, v2.2s
31 urhadd v0.4s, v1.4s, v2.4s
33 // CHECK: urhadd v0.8b, v1.8b, v2.8b // encoding: [0x20,0x14,0x22,0x2e]
34 // CHECK: urhadd v0.16b, v1.16b, v2.16b // encoding: [0x20,0x14,0x22,0x6e]
35 // CHECK: urhadd v0.4h, v1.4h, v2.4h // encoding: [0x20,0x14,0x62,0x2e]
36 // CHECK: urhadd v0.8h, v1.8h, v2.8h // encoding: [0x20,0x14,0x62,0x6e]
37 // CHECK: urhadd v0.2s, v1.2s, v2.2s // encoding: [0x20,0x14,0xa2,0x2e]
38 // CHECK: urhadd v0.4s, v1.4s, v2.4s // encoding: [0x20,0x14,0xa2,0x6e]