test/MC/AMDGPU/hsa-v3.s

   1 // RUN: llvm-mc -mattr=+code-object-v3 -triple amdgcn-amd-amdhsa -mcpu=gfx904 -mattr=+xnack < %s | FileCheck --check-prefix=ASM %s
   2 // RUN: llvm-mc -mattr=+code-object-v3 -triple amdgcn-amd-amdhsa -mcpu=gfx904 -mattr=+xnack -filetype=obj < %s > %t
   3 // RUN: llvm-readelf -sections -symbols -relocations %t | FileCheck --check-prefix=READOBJ %s
   4 // RUN: llvm-objdump -s -j .rodata %t | FileCheck --check-prefix=OBJDUMP %s
   5
   6 // big endian not supported
   7 // XFAIL: host-byteorder-big-endian
   8
   9 // READOBJ: Section Headers
  10 // READOBJ: .text   PROGBITS {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9]+}} AX {{[0-9]+}} {{[0-9]+}} 256
  11 // READOBJ: .rodata PROGBITS {{[0-9a-f]+}} {{[0-9a-f]+}}        0000c0 {{[0-9]+}}  A {{[0-9]+}} {{[0-9]+}} 64
  12
  13 // READOBJ: Relocation section '.rela.rodata' at offset
  14 // READOBJ: 0000000000000010 {{[0-9a-f]+}}00000005 R_AMDGPU_REL64 0000000000000000 .text + 10
  15 // READOBJ: 0000000000000050 {{[0-9a-f]+}}00000005 R_AMDGPU_REL64 0000000000000000 .text + 110
  16 // READOBJ: 0000000000000090 {{[0-9a-f]+}}00000005 R_AMDGPU_REL64 0000000000000000 .text + 210
  17
  18 // READOBJ: Symbol table '.symtab' contains {{[0-9]+}} entries:
  19 // READOBJ: {{[0-9]+}}: 0000000000000100  0 FUNC    LOCAL  PROTECTED 2 complete
  20 // READOBJ: {{[0-9]+}}: 0000000000000040 64 OBJECT  LOCAL  DEFAULT   3 complete.kd
  21 // READOBJ: {{[0-9]+}}: 0000000000000000  0 FUNC    LOCAL  PROTECTED 2 minimal
  22 // READOBJ: {{[0-9]+}}: 0000000000000000 64 OBJECT  LOCAL  DEFAULT   3 minimal.kd
  23 // READOBJ: {{[0-9]+}}: 0000000000000200  0 FUNC    LOCAL  PROTECTED 2 special_sgpr
  24 // READOBJ: {{[0-9]+}}: 0000000000000080 64 OBJECT  LOCAL  DEFAULT   3 special_sgpr.kd
  25
  26 // OBJDUMP: Contents of section .rodata
  27 // Note, relocation for KERNEL_CODE_ENTRY_BYTE_OFFSET is not resolved here.
  28 // minimal
  29 // OBJDUMP-NEXT: 0000 00000000 00000000 00000000 00000000
  30 // OBJDUMP-NEXT: 0010 00000000 00000000 00000000 00000000
  31 // OBJDUMP-NEXT: 0020 00000000 00000000 00000000 00000000
  32 // OBJDUMP-NEXT: 0030 0000ac00 80000000 00000000 00000000
  33 // complete
  34 // OBJDUMP-NEXT: 0040 01000000 01000000 00000000 00000000
  35 // OBJDUMP-NEXT: 0050 00000000 00000000 00000000 00000000
  36 // OBJDUMP-NEXT: 0060 00000000 00000000 00000000 00000000
  37 // OBJDUMP-NEXT: 0070 c2500104 1f0f007f 7f000000 00000000
  38 // special_sgpr
  39 // OBJDUMP-NEXT: 0080 00000000 00000000 00000000 00000000
  40 // OBJDUMP-NEXT: 0090 00000000 00000000 00000000 00000000
  41 // OBJDUMP-NEXT: 00a0 00000000 00000000 00000000 00000000
  42 // OBJDUMP-NEXT: 00b0 00010000 80000000 00000000 00000000
  43
  44 .text
  45 // ASM: .text
  46
  47 .amdgcn_target "amdgcn-amd-amdhsa--gfx904+xnack"
  48 // ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx904+xnack"
  49
  50 .p2align 8
  51 .type minimal,@function
  52 minimal:
  53   s_endpgm
  54
  55 .p2align 8
  56 .type complete,@function
  57 complete:
  58   s_endpgm
  59
  60 .p2align 8
  61 .type special_sgpr,@function
  62 special_sgpr:
  63   s_endpgm
  64
  65 .rodata
  66 // ASM: .rodata
  67
  68 // Test that only specifying required directives is allowed, and that defaulted
  69 // values are omitted.
  70 .p2align 6
  71 .amdhsa_kernel minimal
  72   .amdhsa_next_free_vgpr 0
  73   .amdhsa_next_free_sgpr 0
  74 .end_amdhsa_kernel
  75
  76 // ASM: .amdhsa_kernel minimal
  77 // ASM: .amdhsa_next_free_vgpr 0
  78 // ASM-NEXT: .amdhsa_next_free_sgpr 0
  79 // ASM: .end_amdhsa_kernel
  80
  81 // Test that we can specify all available directives with non-default values.
  82 .p2align 6
  83 .amdhsa_kernel complete
  84   .amdhsa_group_segment_fixed_size 1
  85   .amdhsa_private_segment_fixed_size 1
  86   .amdhsa_user_sgpr_private_segment_buffer 1
  87   .amdhsa_user_sgpr_dispatch_ptr 1
  88   .amdhsa_user_sgpr_queue_ptr 1
  89   .amdhsa_user_sgpr_kernarg_segment_ptr 1
  90   .amdhsa_user_sgpr_dispatch_id 1
  91   .amdhsa_user_sgpr_flat_scratch_init 1
  92   .amdhsa_user_sgpr_private_segment_size 1
  93   .amdhsa_system_sgpr_private_segment_wavefront_offset 1
  94   .amdhsa_system_sgpr_workgroup_id_x 0
  95   .amdhsa_system_sgpr_workgroup_id_y 1
  96   .amdhsa_system_sgpr_workgroup_id_z 1
  97   .amdhsa_system_sgpr_workgroup_info 1
  98   .amdhsa_system_vgpr_workitem_id 1
  99   .amdhsa_next_free_vgpr 9
 100   .amdhsa_next_free_sgpr 27
 101   .amdhsa_reserve_vcc 0
 102   .amdhsa_reserve_flat_scratch 0
 103   .amdhsa_reserve_xnack_mask 0
 104   .amdhsa_float_round_mode_32 1
 105   .amdhsa_float_round_mode_16_64 1
 106   .amdhsa_float_denorm_mode_32 1
 107   .amdhsa_float_denorm_mode_16_64 0
 108   .amdhsa_dx10_clamp 0
 109   .amdhsa_ieee_mode 0
 110   .amdhsa_fp16_overflow 1
 111   .amdhsa_exception_fp_ieee_invalid_op 1
 112   .amdhsa_exception_fp_denorm_src 1
 113   .amdhsa_exception_fp_ieee_div_zero 1
 114   .amdhsa_exception_fp_ieee_overflow 1
 115   .amdhsa_exception_fp_ieee_underflow 1
 116   .amdhsa_exception_fp_ieee_inexact 1
 117   .amdhsa_exception_int_div_zero 1
 118 .end_amdhsa_kernel
 119
 120 // ASM: .amdhsa_kernel complete
 121 // ASM-NEXT: .amdhsa_group_segment_fixed_size 1
 122 // ASM-NEXT: .amdhsa_private_segment_fixed_size 1
 123 // ASM-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
 124 // ASM-NEXT: .amdhsa_user_sgpr_dispatch_ptr 1
 125 // ASM-NEXT: .amdhsa_user_sgpr_queue_ptr 1
 126 // ASM-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 1
 127 // ASM-NEXT: .amdhsa_user_sgpr_dispatch_id 1
 128 // ASM-NEXT: .amdhsa_user_sgpr_flat_scratch_init 1
 129 // ASM-NEXT: .amdhsa_user_sgpr_private_segment_size 1
 130 // ASM-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1
 131 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_x 0
 132 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_y 1
 133 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_z 1
 134 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_info 1
 135 // ASM-NEXT: .amdhsa_system_vgpr_workitem_id 1
 136 // ASM-NEXT: .amdhsa_next_free_vgpr 9
 137 // ASM-NEXT: .amdhsa_next_free_sgpr 27
 138 // ASM-NEXT: .amdhsa_reserve_vcc 0
 139 // ASM-NEXT: .amdhsa_reserve_flat_scratch 0
 140 // ASM-NEXT: .amdhsa_reserve_xnack_mask 0
 141 // ASM-NEXT: .amdhsa_float_round_mode_32 1
 142 // ASM-NEXT: .amdhsa_float_round_mode_16_64 1
 143 // ASM-NEXT: .amdhsa_float_denorm_mode_32 1
 144 // ASM-NEXT: .amdhsa_float_denorm_mode_16_64 0
 145 // ASM-NEXT: .amdhsa_dx10_clamp 0
 146 // ASM-NEXT: .amdhsa_ieee_mode 0
 147 // ASM-NEXT: .amdhsa_fp16_overflow 1
 148 // ASM-NEXT: .amdhsa_exception_fp_ieee_invalid_op 1
 149 // ASM-NEXT: .amdhsa_exception_fp_denorm_src 1
 150 // ASM-NEXT: .amdhsa_exception_fp_ieee_div_zero 1
 151 // ASM-NEXT: .amdhsa_exception_fp_ieee_overflow 1
 152 // ASM-NEXT: .amdhsa_exception_fp_ieee_underflow 1
 153 // ASM-NEXT: .amdhsa_exception_fp_ieee_inexact 1
 154 // ASM-NEXT: .amdhsa_exception_int_div_zero 1
 155 // ASM-NEXT: .end_amdhsa_kernel
 156
 157 // Test that we are including special SGPR usage in the granulated count.
 158 .p2align 6
 159 .amdhsa_kernel special_sgpr
 160   // Same next_free_sgpr as "complete", but...
 161   .amdhsa_next_free_sgpr 27
 162   // ...on GFX9 this should require an additional 6 SGPRs, pushing us from
 163   // 3 granules to 4
 164   .amdhsa_reserve_flat_scratch 1
 165
 166   .amdhsa_reserve_vcc 0
 167   .amdhsa_reserve_xnack_mask 0
 168
 169   .amdhsa_float_denorm_mode_16_64 0
 170   .amdhsa_dx10_clamp 0
 171   .amdhsa_ieee_mode 0
 172   .amdhsa_next_free_vgpr 0
 173 .end_amdhsa_kernel
 174
 175 // ASM: .amdhsa_kernel special_sgpr
 176 // ASM: .amdhsa_next_free_vgpr 0
 177 // ASM-NEXT: .amdhsa_next_free_sgpr 27
 178 // ASM-NEXT: .amdhsa_reserve_vcc 0
 179 // ASM-NEXT: .amdhsa_reserve_xnack_mask 0
 180 // ASM: .amdhsa_float_denorm_mode_16_64 0
 181 // ASM-NEXT: .amdhsa_dx10_clamp 0
 182 // ASM-NEXT: .amdhsa_ieee_mode 0
 183 // ASM: .end_amdhsa_kernel
 184
 185 .section .foo
 186
 187 .byte .amdgcn.gfx_generation_number
 188 // ASM: .byte 9
 189
 190 .byte .amdgcn.gfx_generation_minor
 191 // ASM: .byte 0
 192
 193 .byte .amdgcn.gfx_generation_stepping
 194 // ASM: .byte 4
 195
 196 .byte .amdgcn.next_free_vgpr
 197 // ASM: .byte 0
 198 .byte .amdgcn.next_free_sgpr
 199 // ASM: .byte 0
 200
 201 v_mov_b32_e32 v7, s10
 202
 203 .byte .amdgcn.next_free_vgpr
 204 // ASM: .byte 8
 205 .byte .amdgcn.next_free_sgpr
 206 // ASM: .byte 11
 207
 208 .set .amdgcn.next_free_vgpr, 0
 209 .set .amdgcn.next_free_sgpr, 0
 210
 211 .byte .amdgcn.next_free_vgpr
 212 // ASM: .byte 0
 213 .byte .amdgcn.next_free_sgpr
 214 // ASM: .byte 0
 215
 216 v_mov_b32_e32 v16, s3
 217
 218 .byte .amdgcn.next_free_vgpr
 219 // ASM: .byte 17
 220 .byte .amdgcn.next_free_sgpr
 221 // ASM: .byte 4
 222
 223 // Metadata
 224
 225 .amdgpu_metadata
 226   amdhsa.version:
 227     - 3
 228     - 0
 229   amdhsa.kernels:
 230     - .name:       amd_kernel_code_t_test_all
 231       .symbol: amd_kernel_code_t_test_all@kd
 232       .kernarg_segment_size: 8
 233       .group_segment_fixed_size: 16
 234       .private_segment_fixed_size: 32
 235       .kernarg_segment_align: 64
 236       .wavefront_size: 128
 237       .sgpr_count: 14
 238       .vgpr_count: 40
 239       .max_flat_workgroup_size: 256
 240     - .name:       amd_kernel_code_t_minimal
 241       .symbol: amd_kernel_code_t_minimal@kd
 242       .kernarg_segment_size: 8
 243       .group_segment_fixed_size: 16
 244       .private_segment_fixed_size: 32
 245       .kernarg_segment_align: 64
 246       .wavefront_size: 128
 247       .sgpr_count: 14
 248       .vgpr_count: 40
 249       .max_flat_workgroup_size: 256
 250 .end_amdgpu_metadata
 251
 252 // ASM:         .amdgpu_metadata
 253 // ASM:      amdhsa.kernels:
 254 // ASM:        - .group_segment_fixed_size: 16
 255 // ASM:          .kernarg_segment_align: 64
 256 // ASM:          .kernarg_segment_size: 8
 257 // ASM:          .max_flat_workgroup_size: 256
 258 // ASM:          .name:           amd_kernel_code_t_test_all
 259 // ASM:          .private_segment_fixed_size: 32
 260 // ASM:          .sgpr_count:     14
 261 // ASM:          .symbol:         'amd_kernel_code_t_test_all@kd'
 262 // ASM:          .vgpr_count:     40
 263 // ASM:          .wavefront_size: 128
 264 // ASM:        - .group_segment_fixed_size: 16
 265 // ASM:          .kernarg_segment_align: 64
 266 // ASM:          .kernarg_segment_size: 8
 267 // ASM:          .max_flat_workgroup_size: 256
 268 // ASM:          .name:           amd_kernel_code_t_minimal
 269 // ASM:          .private_segment_fixed_size: 32
 270 // ASM:          .sgpr_count:     14
 271 // ASM:          .symbol:         'amd_kernel_code_t_minimal@kd'
 272 // ASM:          .vgpr_count:     40
 273 // ASM:          .wavefront_size: 128
 274 // ASM:      amdhsa.version:
 275 // ASM-NEXT:   - 3
 276 // ASM-NEXT:   - 0
 277 // ASM:         .end_amdgpu_metadata