[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AMDGPU / sopk-err.s
blob7d1bd8110b5d83fe94704992961333042f771086
1 // RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=GCN %s
2 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=SI-ERR %s
3 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI-ERR %s
4 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GFX9-ERR %s
5 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX9 %s
6 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX10 %s
8 s_setreg_b32 0x1f803, s2
9 // GCN: error: invalid immediate: only 16-bit values are legal
11 s_setreg_b32 typo(0x40), s2
12 // GCN: error: expected absolute expression
14 s_setreg_b32 hwreg(0x40), s2
15 // GCN: error: invalid code of hardware register: only 6-bit values are legal
17 s_setreg_b32 hwreg(HW_REG_WRONG), s2
18 // GCN: error: expected absolute expression
20 s_setreg_b32 hwreg(1 2,3), s2
21 // GCN: error: expected a comma or a closing parenthesis
23 s_setreg_b32 hwreg(1,2 3), s2
24 // GCN: error: expected a comma
26 s_setreg_b32 hwreg(1,2,3, s2
27 // GCN: error: expected a closing parenthesis
29 s_setreg_b32 hwreg(3,32,32), s2
30 // GCN: error: invalid bit offset: only 5-bit values are legal
32 s_setreg_b32 hwreg(3,0,33), s2
33 // GCN: error: invalid bitfield width: only values from 1 to 32 are legal
35 s_setreg_imm32_b32 0x1f803, 0xff
36 // GCN: error: invalid immediate: only 16-bit values are legal
38 s_setreg_imm32_b32 hwreg(3,0,33), 0xff
39 // GCN: error: invalid bitfield width: only values from 1 to 32 are legal
41 s_getreg_b32 s2, hwreg(3,32,32)
42 // GCN: error: invalid bit offset: only 5-bit values are legal
44 s_cbranch_i_fork s[2:3], 0x6
45 // GFX10: error: instruction not supported on this GPU
47 s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES)
48 // SI-ERR: specified hardware register is not supported on this GPU
49 // VI-ERR: specified hardware register is not supported on this GPU
50 // GFX9: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x82,0xb8]
51 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x02,0xb9]
53 s_getreg_b32 s2, hwreg(HW_REG_TBA_LO)
54 // SI-ERR: specified hardware register is not supported on this GPU
55 // VI-ERR: specified hardware register is not supported on this GPU
56 // GFX9-ERR: specified hardware register is not supported on this GPU
57 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x02,0xb9]
59 s_getreg_b32 s2, hwreg(HW_REG_TBA_HI)
60 // SI-ERR: specified hardware register is not supported on this GPU
61 // VI-ERR: specified hardware register is not supported on this GPU
62 // GFX9-ERR: specified hardware register is not supported on this GPU
63 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x02,0xb9]
65 s_getreg_b32 s2, hwreg(HW_REG_TMA_LO)
66 // SI-ERR: specified hardware register is not supported on this GPU
67 // VI-ERR: specified hardware register is not supported on this GPU
68 // GFX9-ERR: specified hardware register is not supported on this GPU
69 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x02,0xb9]
71 s_getreg_b32 s2, hwreg(HW_REG_TMA_HI)
72 // SI-ERR: specified hardware register is not supported on this GPU
73 // VI-ERR: specified hardware register is not supported on this GPU
74 // GFX9-ERR: specified hardware register is not supported on this GPU
75 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x02,0xb9]
77 s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO)
78 // SI-ERR: specified hardware register is not supported on this GPU
79 // VI-ERR: specified hardware register is not supported on this GPU
80 // GFX9-ERR: specified hardware register is not supported on this GPU
81 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) ; encoding: [0x14,0xf8,0x02,0xb9]
83 s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_HI)
84 // SI-ERR: specified hardware register is not supported on this GPU
85 // VI-ERR: specified hardware register is not supported on this GPU
86 // GFX9-ERR: specified hardware register is not supported on this GPU
87 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_HI) ; encoding: [0x15,0xf8,0x02,0xb9]
89 s_getreg_b32 s2, hwreg(HW_REG_XNACK_MASK)
90 // SI-ERR: specified hardware register is not supported on this GPU
91 // VI-ERR: specified hardware register is not supported on this GPU
92 // GFX9-ERR: specified hardware register is not supported on this GPU
93 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_XNACK_MASK) ; encoding: [0x16,0xf8,0x02,0xb9]
95 s_getreg_b32 s2, hwreg(HW_REG_POPS_PACKER)
96 // SI-ERR: specified hardware register is not supported on this GPU
97 // VI-ERR: specified hardware register is not supported on this GPU
98 // GFX9-ERR: specified hardware register is not supported on this GPU
99 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_POPS_PACKER) ; encoding: [0x19,0xf8,0x02,0xb9]
101 s_cmpk_le_u32 s2, -1
102 // GCN: error: invalid operand for instruction
104 s_cmpk_le_u32 s2, 0x1ffff
105 // GCN: error: invalid operand for instruction
107 s_cmpk_le_u32 s2, 0x10000
108 // GCN: error: invalid operand for instruction
110 s_mulk_i32 s2, 0xFFFFFFFFFFFF0000
111 // GCN: error: invalid operand for instruction
113 s_mulk_i32 s2, 0x10000
114 // GCN: error: invalid operand for instruction