[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / ARM / invalid-addsub.s
blob07c1a800425121efa0402e37fa640d9107025d01
1 @ RUN: not llvm-mc -triple thumbv7-apple-ios %s -o - 2>&1 | FileCheck %s
3 @ CHECK: error: source register must be sp if destination is sp
4 @ CHECK: error: source register must be sp if destination is sp
5 @ CHECK: error: source register must be sp if destination is sp
6 @ CHECK: error: source register must be sp if destination is sp
7 add sp, r5, #1
8 addw sp, r7, #4
9 add sp, r3, r2
10 add sp, r3, r5, lsl #3
13 @ CHECK: error: source register must be sp if destination is sp
14 @ CHECK: error: source register must be sp if destination is sp
15 @ CHECK: error: source register must be sp if destination is sp
16 @ CHECK: error: source register must be sp if destination is sp
17 sub sp, r5, #1
18 subw sp, r7, #4
19 sub sp, r3, r2
20 sub sp, r3, r5, lsl #3