[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / ARM / negative-immediates-thumb1.s
blob1fc9a1e7c20547b0f8c30f1a75ad322bed18cb7f
1 # RUN: llvm-mc -triple thumbv7 -mcpu=cortex-m0 %s -show-encoding | FileCheck %s
2 # RUN: not llvm-mc -triple thumbv7 -mcpu=cortex-m0 %s -show-encoding -mattr=+no-neg-immediates 2>&1 | FileCheck %s -check-prefix=CHECK-DISABLED
4 .thumb
6 ADDs r1, r0, #0xFFFFFFF9
7 # CHECK: subs r1, r0, #7
8 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
9 ADDs r0, #0xFFFFFF01
10 # CHECK: subs r0, #255
11 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
13 SUBs r0, #0xFFFFFF01
14 # CHECK: adds r0, #255
15 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
17 SUBs r1, r0, #0xFFFFFFF9
18 # CHECK: adds r1, r0, #7
19 # CHECK-DISABLED: note: instruction requires: NegativeImmediates