[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / Mips / nacl-mask.s
blobe7eba3769ac05580b6892de507504b580e92d719
1 # RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-nacl %s \
2 # RUN: | llvm-objdump -disassemble -z -no-show-raw-insn - | FileCheck %s
4 # This test tests that address-masking sandboxing is added when given assembly
5 # input.
8 # Test that address-masking sandboxing is added before indirect branches and
9 # returns.
11 .align 4
12 test1:
13 .set noreorder
15 jr $a0
16 nop
17 jr $ra
18 nop
20 # CHECK-LABEL: test1:
22 # CHECK: and $4, $4, $14
23 # CHECK-NEXT: jr $4
25 # Check that additional nop is inserted, to align mask and jr to the next
26 # bundle.
28 # CHECK-NEXT: nop
29 # CHECK-NEXT: nop
31 # CHECK: and $ra, $ra, $14
32 # CHECK-NEXT: jr $ra
36 # Test that address-masking sandboxing is added before load instructions.
38 .align 4
39 test2:
40 .set noreorder
42 lb $4, 0($1)
43 nop
44 lbu $4, 0($2)
45 lh $4, 0($3)
46 lhu $1, 0($4)
47 lw $4, 0($5)
48 lwc1 $f0, 0($6)
49 ldc1 $f2, 0($7)
50 ll $4, 0($8)
51 lwl $4, 0($9)
52 lwr $4, 0($10)
54 lw $4, 0($sp)
55 lw $4, 0($t8)
57 # CHECK-LABEL: test2:
59 # CHECK: and $1, $1, $15
60 # CHECK-NEXT: lb $4, 0($1)
62 # Check that additional nop is inserted, to align mask and load to the next
63 # bundle.
65 # CHECK: nop
66 # CHECK: nop
68 # CHECK: and $2, $2, $15
69 # CHECK-NEXT: lbu $4, 0($2)
71 # CHECK: and $3, $3, $15
72 # CHECK-NEXT: lh $4, 0($3)
74 # CHECK: and $4, $4, $15
75 # CHECK-NEXT: lhu $1, 0($4)
77 # CHECK: and $5, $5, $15
78 # CHECK-NEXT: lw $4, 0($5)
80 # CHECK: and $6, $6, $15
81 # CHECK-NEXT: lwc1 $f0, 0($6)
83 # CHECK: and $7, $7, $15
84 # CHECK-NEXT: ldc1 $f2, 0($7)
86 # CHECK: and $8, $8, $15
87 # CHECK-NEXT: ll $4, 0($8)
89 # CHECK: and $9, $9, $15
90 # CHECK-NEXT: lwl $4, 0($9)
92 # CHECK: and $10, $10, $15
93 # CHECK-NEXT: lwr $4, 0($10)
96 # Check that loads where base register is $sp or $t8 (thread pointer register)
97 # are not masked.
99 # CHECK-NOT: and
100 # CHECK: lw $4, 0($sp)
101 # CHECK-NOT: and
102 # CHECK: lw $4, 0($24)
106 # Test that address-masking sandboxing is added before store instructions.
108 .align 4
109 test3:
110 .set noreorder
112 sb $4, 0($1)
114 sh $4, 0($2)
115 sw $4, 0($3)
116 swc1 $f0, 0($4)
117 sdc1 $f2, 0($5)
118 swl $4, 0($6)
119 swr $4, 0($7)
120 sc $4, 0($8)
122 sw $4, 0($sp)
123 sw $4, 0($t8)
125 # CHECK-LABEL: test3:
127 # CHECK: and $1, $1, $15
128 # CHECK-NEXT: sb $4, 0($1)
130 # Check that additional nop is inserted, to align mask and store to the next
131 # bundle.
133 # CHECK: nop
134 # CHECK: nop
136 # CHECK: and $2, $2, $15
137 # CHECK-NEXT: sh $4, 0($2)
139 # CHECK: and $3, $3, $15
140 # CHECK-NEXT: sw $4, 0($3)
142 # CHECK: and $4, $4, $15
143 # CHECK-NEXT: swc1 $f0, 0($4)
145 # CHECK: and $5, $5, $15
146 # CHECK-NEXT: sdc1 $f2, 0($5)
148 # CHECK: and $6, $6, $15
149 # CHECK-NEXT: swl $4, 0($6)
151 # CHECK: and $7, $7, $15
152 # CHECK-NEXT: swr $4, 0($7)
154 # CHECK: and $8, $8, $15
155 # CHECK-NEXT: sc $4, 0($8)
158 # Check that stores where base register is $sp or $t8 (thread pointer register)
159 # are not masked.
161 # CHECK-NOT: and
162 # CHECK: sw $4, 0($sp)
163 # CHECK-NOT: and
164 # CHECK: sw $4, 0($24)
168 # Test that address-masking sandboxing is added after instructions that change
169 # stack pointer.
171 .align 4
172 test4:
173 .set noreorder
175 addiu $sp, $sp, 24
177 addu $sp, $sp, $1
178 lw $sp, 0($2)
179 lw $sp, 123($sp)
180 sw $sp, 123($sp)
182 # CHECK-LABEL: test4:
184 # CHECK: addiu $sp, $sp, 24
185 # CHECK-NEXT: and $sp, $sp, $15
187 # Check that additional nop is inserted, to align instruction and mask to the
188 # next bundle.
190 # CHECK: nop
191 # CHECK: nop
193 # CHECK: addu $sp, $sp, $1
194 # CHECK-NEXT: and $sp, $sp, $15
196 # Since we next check sandboxing sequence which consists of 3 instructions,
197 # check that 2 additional nops are inserted, to align it to the next bundle.
199 # CHECK: nop
200 # CHECK: nop
203 # Check that for instructions that change stack-pointer and load from memory
204 # masks are added before and after the instruction.
206 # CHECK: and $2, $2, $15
207 # CHECK-NEXT: lw $sp, 0($2)
208 # CHECK-NEXT: and $sp, $sp, $15
210 # For loads where $sp is destination and base, check that mask is added after
211 # but not before.
213 # CHECK-NOT: and
214 # CHECK: lw $sp, 123($sp)
215 # CHECK-NEXT: and $sp, $sp, $15
217 # For stores where $sp is destination and base, check that mask is added neither
218 # before nor after.
220 # CHECK-NOT: and
221 # CHECK: sw $sp, 123($sp)
222 # CHECK-NOT: and
226 # Test that call + branch delay is aligned at bundle end. Test that mask is
227 # added before indirect calls.
229 .align 4
230 test5:
231 .set noreorder
233 jal func1
234 addiu $4, $zero, 1
237 bal func2
238 addiu $4, $zero, 2
242 bltzal $t1, func3
243 addiu $4, $zero, 3
248 bgezal $t2, func4
249 addiu $4, $zero, 4
251 jalr $t9
252 addiu $4, $zero, 5
255 # CHECK: nop
256 # CHECK-NEXT: nop
257 # CHECK-LABEL: test5:
258 # CHECK-NEXT: jal
259 # CHECK-NEXT: addiu $4, $zero, 1
261 # CHECK-NEXT: nop
262 # CHECK-NEXT: nop
263 # CHECK-NEXT: bal
264 # CHECK-NEXT: addiu $4, $zero, 2
266 # CHECK-NEXT: nop
267 # CHECK-NEXT: nop
268 # CHECK-NEXT: bltzal
269 # CHECK-NEXT: addiu $4, $zero, 3
271 # CHECK-NEXT: nop
272 # CHECK-NEXT: nop
273 # CHECK-NEXT: nop
274 # CHECK-NEXT: nop
276 # CHECK-NEXT: nop
277 # CHECK-NEXT: nop
278 # CHECK-NEXT: bgezal
279 # CHECK-NEXT: addiu $4, $zero, 4
281 # CHECK-NEXT: nop
282 # CHECK-NEXT: and $25, $25, $14
283 # CHECK-NEXT: jalr $25
284 # CHECK-NEXT: addiu $4, $zero, 5
288 # Test that we can put non-dangerous loads and stores in branch delay slot.
290 .align 4
291 test6:
292 .set noreorder
294 jal func1
295 sw $4, 0($sp)
297 bal func2
298 lw $5, 0($t8)
300 jalr $t9
301 sw $sp, 0($sp)
305 # CHECK: nop
306 # CHECK-NEXT: nop
307 # CHECK-LABEL: test6:
308 # CHECK-NEXT: jal
309 # CHECK-NEXT: sw $4, 0($sp)
311 # CHECK-NEXT: nop
312 # CHECK-NEXT: nop
313 # CHECK-NEXT: bal
314 # CHECK-NEXT: lw $5, 0($24)
316 # CHECK-NEXT: nop
317 # CHECK-NEXT: and $25, $25, $14
318 # CHECK-NEXT: jalr
319 # CHECK-NEXT: sw $sp, 0($sp)