1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt < %s -indvars -S | FileCheck %s
4 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:1"
6 ; We make a transform by getting rid of add nsw i32 %tmp17, -1; make sure that
7 ; we drop "exact" flag on lshr as we do it.
8 define void @drop_exact(i32* %p, i64* %p1) {
9 ; CHECK-LABEL: @drop_exact(
11 ; CHECK-NEXT: br label [[BB12:%.*]]
13 ; CHECK-NEXT: ret void
15 ; CHECK-NEXT: [[TMP13:%.*]] = phi i32 [ -47436, [[BB:%.*]] ], [ [[TMP15:%.*]], [[BB12]] ]
16 ; CHECK-NEXT: [[TMP14:%.*]] = phi i32 [ 0, [[BB]] ], [ [[TMP42:%.*]], [[BB12]] ]
17 ; CHECK-NEXT: [[TMP15]] = add nsw i32 [[TMP13]], -1
18 ; CHECK-NEXT: [[TMP16:%.*]] = shl i32 [[TMP15]], 1
19 ; CHECK-NEXT: [[TMP17:%.*]] = sub nsw i32 42831, [[TMP16]]
20 ; CHECK-NEXT: [[TMP19:%.*]] = lshr i32 [[TMP17]], 1
21 ; CHECK-NEXT: [[TMP20:%.*]] = urem i32 [[TMP19]], 250
22 ; CHECK-NEXT: [[TMP22:%.*]] = lshr i32 [[TMP17]], 1
23 ; CHECK-NEXT: store i32 [[TMP22]], i32* [[P:%.*]], align 4
24 ; CHECK-NEXT: [[TMP26:%.*]] = zext i32 [[TMP20]] to i64
25 ; CHECK-NEXT: store i64 [[TMP26]], i64* [[P1:%.*]], align 4
26 ; CHECK-NEXT: [[TMP42]] = add nuw nsw i32 [[TMP14]], 1
27 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[TMP42]], 719
28 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[BB7:%.*]], label [[BB12]]
36 bb12: ; preds = %bb12, %bb
37 %tmp13 = phi i32 [ -47436, %bb ], [ %tmp15, %bb12 ]
38 %tmp14 = phi i32 [ 0, %bb ], [ %tmp42, %bb12 ]
39 %tmp15 = add i32 %tmp13, -1
40 %tmp16 = shl i32 %tmp15, 1
41 %tmp17 = sub i32 42831, %tmp16
42 %tmp19 = lshr i32 %tmp17, 1
43 %tmp20 = urem i32 %tmp19, 250
44 %tmp21 = add nsw i32 %tmp17, -1
45 %tmp22 = lshr exact i32 %tmp21, 1
46 store i32 %tmp22, i32* %p, align 4
47 %tmp26 = zext i32 %tmp20 to i64
48 store i64 %tmp26, i64* %p1, align 4
49 %tmp42 = add nuw nsw i32 %tmp14, 1
50 %tmp43 = icmp ugt i32 %tmp14, 717
51 br i1 %tmp43, label %bb7, label %bb12
54 ; Throw away add nsw i32 %tmp17, 0, do not drop exact flag.
55 define void @dont_drop_exact(i32* %p, i64* %p1) {
56 ; CHECK-LABEL: @dont_drop_exact(
58 ; CHECK-NEXT: br label [[BB12:%.*]]
60 ; CHECK-NEXT: ret void
62 ; CHECK-NEXT: [[TMP13:%.*]] = phi i32 [ -47436, [[BB:%.*]] ], [ [[TMP15:%.*]], [[BB12]] ]
63 ; CHECK-NEXT: [[TMP14:%.*]] = phi i32 [ 0, [[BB]] ], [ [[TMP42:%.*]], [[BB12]] ]
64 ; CHECK-NEXT: [[TMP15]] = add nsw i32 [[TMP13]], -1
65 ; CHECK-NEXT: [[TMP16:%.*]] = shl i32 [[TMP15]], 1
66 ; CHECK-NEXT: [[TMP17:%.*]] = sub nsw i32 42831, [[TMP16]]
67 ; CHECK-NEXT: [[TMP19:%.*]] = lshr i32 [[TMP17]], 1
68 ; CHECK-NEXT: [[TMP20:%.*]] = urem i32 [[TMP19]], 250
69 ; CHECK-NEXT: [[TMP22:%.*]] = lshr exact i32 [[TMP17]], 1
70 ; CHECK-NEXT: store i32 [[TMP22]], i32* [[P:%.*]], align 4
71 ; CHECK-NEXT: [[TMP26:%.*]] = zext i32 [[TMP20]] to i64
72 ; CHECK-NEXT: store i64 [[TMP26]], i64* [[P1:%.*]], align 4
73 ; CHECK-NEXT: [[TMP42]] = add nuw nsw i32 [[TMP14]], 1
74 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[TMP42]], 719
75 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[BB7:%.*]], label [[BB12]]
83 bb12: ; preds = %bb12, %bb
84 %tmp13 = phi i32 [ -47436, %bb ], [ %tmp15, %bb12 ]
85 %tmp14 = phi i32 [ 0, %bb ], [ %tmp42, %bb12 ]
86 %tmp15 = add i32 %tmp13, -1
87 %tmp16 = shl i32 %tmp15, 1
88 %tmp17 = sub i32 42831, %tmp16
89 %tmp19 = lshr i32 %tmp17, 1
90 %tmp20 = urem i32 %tmp19, 250
91 %tmp21 = add nsw i32 %tmp17, 0
92 %tmp22 = lshr exact i32 %tmp21, 1
93 store i32 %tmp22, i32* %p, align 4
94 %tmp26 = zext i32 %tmp20 to i64
95 store i64 %tmp26, i64* %p1, align 4
96 %tmp42 = add nuw nsw i32 %tmp14, 1
97 %tmp43 = icmp ugt i32 %tmp14, 717
98 br i1 %tmp43, label %bb7, label %bb12