1 ; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
3 ; These tests would be improved by 'movs r0, #0' being rematerialized below the
4 ; test as 'mov.w r0, #0'.
7 define i32 @f2(i32 %a) {
9 %tmp1 = icmp eq i32 0, %tmp
10 %ret = select i1 %tmp1, i32 42, i32 24
14 ; CHECK: teq.w {{.*}}, #187
16 ; 0x00aa00aa = 11141290
17 define i32 @f3(i32 %a) {
18 %tmp = xor i32 %a, 11141290
19 %tmp1 = icmp eq i32 %tmp, 0
20 %ret = select i1 %tmp1, i32 42, i32 24
24 ; CHECK: teq.w {{.*}}, #11141290
26 ; 0xcc00cc00 = 3422604288
27 define i32 @f6(i32 %a) {
28 %tmp = xor i32 %a, 3422604288
29 %tmp1 = icmp eq i32 0, %tmp
30 %ret = select i1 %tmp1, i32 42, i32 24
34 ; CHECK: teq.w {{.*}}, #-872363008
36 ; 0xdddddddd = 3722304989
37 define i32 @f7(i32 %a) {
38 %tmp = xor i32 %a, 3722304989
39 %tmp1 = icmp eq i32 %tmp, 0
40 %ret = select i1 %tmp1, i32 42, i32 24
44 ; CHECK: teq.w {{.*}}, #-572662307
46 ; 0x00110000 = 1114112
47 define i32 @f10(i32 %a) {
48 %tmp = xor i32 %a, 1114112
49 %tmp1 = icmp eq i32 0, %tmp
50 %ret = select i1 %tmp1, i32 42, i32 24
54 ; CHECK: teq.w {{.*}}, #1114112
57 define i1 @f12(i32 %a) {
58 %tmp = xor i32 %a, 187
59 %tmp1 = icmp eq i32 0, %tmp
63 ; CHECK: eor r0, r0, #187
64 ; CHECK-NEXT: clz r0, r0
65 ; CHECK-NEXT: lsrs r0, r0, #5
67 ; 0x00aa00aa = 11141290
68 define i1 @f13(i32 %a) {
69 %tmp = xor i32 %a, 11141290
70 %tmp1 = icmp eq i32 %tmp, 0
74 ; CHECK: eor r0, r0, #11141290
75 ; CHECK-NEXT: clz r0, r0
76 ; CHECK-NEXT: lsrs r0, r0, #5
78 ; 0xcc00cc00 = 3422604288
79 define i1 @f16(i32 %a) {
80 %tmp = xor i32 %a, 3422604288
81 %tmp1 = icmp eq i32 0, %tmp
85 ; CHECK: eor r0, r0, #-872363008
86 ; CHECK-NEXT: clz r0, r0
87 ; CHECK-NEXT: lsrs r0, r0, #5
89 ; 0xdddddddd = 3722304989
90 define i1 @f17(i32 %a) {
91 %tmp = xor i32 %a, 3722304989
92 %tmp1 = icmp eq i32 %tmp, 0
96 ; CHECK: eor r0, r0, #-572662307
97 ; CHECK-NEXT: clz r0, r0
98 ; CHECK-NEXT: lsrs r0, r0, #5
100 ; 0x00110000 = 1114112
101 define i1 @f18(i32 %a) {
102 %tmp = xor i32 %a, 1114112
103 %tmp1 = icmp eq i32 0, %tmp
107 ; CHECK: eor r0, r0, #1114112
108 ; CHECK-NEXT: clz r0, r0
109 ; CHECK-NEXT: lsrs r0, r0, #5