1 set(LLVM_TARGET_DEFINITIONS RISCV.td)
3 tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
4 tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
5 tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter)
6 tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
7 tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
8 tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
9 tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
10 tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
11 tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
12 tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
13 tablegen(LLVM RISCVGenSystemOperands.inc -gen-searchable-tables)
15 add_public_tablegen_target(RISCVCommonTableGen)
17 add_llvm_target(RISCVCodeGen
19 RISCVExpandPseudoInsts.cpp
20 RISCVFrameLowering.cpp
25 RISCVMergeBaseOffset.cpp
28 RISCVTargetMachine.cpp
29 RISCVTargetObjectFile.cpp
30 RISCVTargetTransformInfo.cpp
33 add_subdirectory(AsmParser)
34 add_subdirectory(Disassembler)
35 add_subdirectory(MCTargetDesc)
36 add_subdirectory(TargetInfo)
37 add_subdirectory(Utils)