[ARM] MVE integer min and max
[llvm-core.git] / lib / Target / RISCV / CMakeLists.txt
blob5cdaf344703b2dbc6433f37a37eb89650c24ef0f
1 set(LLVM_TARGET_DEFINITIONS RISCV.td)
3 tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
4 tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
5 tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter)
6 tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
7 tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
8 tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
9 tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
10 tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
11 tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
12 tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
13 tablegen(LLVM RISCVGenSystemOperands.inc -gen-searchable-tables)
15 add_public_tablegen_target(RISCVCommonTableGen)
17 add_llvm_target(RISCVCodeGen
18   RISCVAsmPrinter.cpp
19   RISCVExpandPseudoInsts.cpp
20   RISCVFrameLowering.cpp
21   RISCVInstrInfo.cpp
22   RISCVISelDAGToDAG.cpp
23   RISCVISelLowering.cpp
24   RISCVMCInstLower.cpp
25   RISCVMergeBaseOffset.cpp
26   RISCVRegisterInfo.cpp
27   RISCVSubtarget.cpp
28   RISCVTargetMachine.cpp
29   RISCVTargetObjectFile.cpp
30   RISCVTargetTransformInfo.cpp
31   )
33 add_subdirectory(AsmParser)
34 add_subdirectory(Disassembler)
35 add_subdirectory(MCTargetDesc)
36 add_subdirectory(TargetInfo)
37 add_subdirectory(Utils)