[ARM] MVE integer min and max
[llvm-core.git] / lib / Target / RISCV / MCTargetDesc / RISCVFixupKinds.h
blob6c7933340608b36dde162bde446660f037be2b2c
1 //===-- RISCVFixupKinds.h - RISCV Specific Fixup Entries --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVFIXUPKINDS_H
10 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVFIXUPKINDS_H
12 #include "llvm/MC/MCFixup.h"
14 #undef RISCV
16 namespace llvm {
17 namespace RISCV {
18 enum Fixups {
19 // fixup_riscv_hi20 - 20-bit fixup corresponding to hi(foo) for
20 // instructions like lui
21 fixup_riscv_hi20 = FirstTargetFixupKind,
22 // fixup_riscv_lo12_i - 12-bit fixup corresponding to lo(foo) for
23 // instructions like addi
24 fixup_riscv_lo12_i,
25 // fixup_riscv_lo12_s - 12-bit fixup corresponding to lo(foo) for
26 // the S-type store instructions
27 fixup_riscv_lo12_s,
28 // fixup_riscv_pcrel_hi20 - 20-bit fixup corresponding to pcrel_hi(foo) for
29 // instructions like auipc
30 fixup_riscv_pcrel_hi20,
31 // fixup_riscv_pcrel_lo12_i - 12-bit fixup corresponding to pcrel_lo(foo) for
32 // instructions like addi
33 fixup_riscv_pcrel_lo12_i,
34 // fixup_riscv_pcrel_lo12_s - 12-bit fixup corresponding to pcrel_lo(foo) for
35 // the S-type store instructions
36 fixup_riscv_pcrel_lo12_s,
37 // fixup_riscv_got_hi20 - 20-bit fixup corresponding to got_pcrel_hi(foo) for
38 // instructions like auipc
39 fixup_riscv_got_hi20,
40 // fixup_riscv_tprel_hi20 - 20-bit fixup corresponding to tprel_hi(foo) for
41 // instructions like lui
42 fixup_riscv_tprel_hi20,
43 // fixup_riscv_tprel_lo12_i - 12-bit fixup corresponding to tprel_lo(foo) for
44 // instructions like addi
45 fixup_riscv_tprel_lo12_i,
46 // fixup_riscv_tprel_lo12_s - 12-bit fixup corresponding to tprel_lo(foo) for
47 // the S-type store instructions
48 fixup_riscv_tprel_lo12_s,
49 // fixup_riscv_tprel_add - A fixup corresponding to %tprel_add(foo) for the
50 // add_tls instruction. Used to provide a hint to the linker.
51 fixup_riscv_tprel_add,
52 // fixup_riscv_tls_got_hi20 - 20-bit fixup corresponding to
53 // tls_ie_pcrel_hi(foo) for instructions like auipc
54 fixup_riscv_tls_got_hi20,
55 // fixup_riscv_tls_gd_hi20 - 20-bit fixup corresponding to
56 // tls_gd_pcrel_hi(foo) for instructions like auipc
57 fixup_riscv_tls_gd_hi20,
58 // fixup_riscv_jal - 20-bit fixup for symbol references in the jal
59 // instruction
60 fixup_riscv_jal,
61 // fixup_riscv_branch - 12-bit fixup for symbol references in the branch
62 // instructions
63 fixup_riscv_branch,
64 // fixup_riscv_rvc_jump - 11-bit fixup for symbol references in the
65 // compressed jump instruction
66 fixup_riscv_rvc_jump,
67 // fixup_riscv_rvc_branch - 8-bit fixup for symbol references in the
68 // compressed branch instruction
69 fixup_riscv_rvc_branch,
70 // fixup_riscv_call - A fixup representing a call attached to the auipc
71 // instruction in a pair composed of adjacent auipc+jalr instructions.
72 fixup_riscv_call,
73 // fixup_riscv_call_plt - A fixup representing a procedure linkage table call
74 // attached to the auipc instruction in a pair composed of adjacent auipc+jalr
75 // instructions.
76 fixup_riscv_call_plt,
77 // fixup_riscv_relax - Used to generate an R_RISCV_RELAX relocation type,
78 // which indicates the linker may relax the instruction pair.
79 fixup_riscv_relax,
80 // fixup_riscv_align - Used to generate an R_RISCV_ALIGN relocation type,
81 // which indicates the linker should fixup the alignment after linker
82 // relaxation.
83 fixup_riscv_align,
85 // fixup_riscv_invalid - used as a sentinel and a marker, must be last fixup
86 fixup_riscv_invalid,
87 NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind
89 } // end namespace RISCV
90 } // end namespace llvm
92 #endif