lib/Target/X86/X86SchedHaswell.td

   1 //=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the machine model for Haswell to support instruction
  10 // scheduling and other instruction cost heuristics.
  11 //
  12 // Note that we define some instructions here that are not supported by haswell,
  13 // but we still have to define them because KNL uses the HSW model.
  14 // They are currently tagged with a comment `Unsupported = 1`.
  15 // FIXME: Use Unsupported = 1 once KNL has its own model.
  16 //
  17 //===----------------------------------------------------------------------===//
  18
  19 def HaswellModel : SchedMachineModel {
  20   // All x86 instructions are modeled as a single micro-op, and HW can decode 4
  21   // instructions per cycle.
  22   let IssueWidth = 4;
  23   let MicroOpBufferSize = 192; // Based on the reorder buffer.
  24   let LoadLatency = 5;
  25   let MispredictPenalty = 16;
  26
  27   // Based on the LSD (loop-stream detector) queue size and benchmarking data.
  28   let LoopMicroOpBufferSize = 50;
  29
  30   // This flag is set to allow the scheduler to assign a default model to
  31   // unrecognized opcodes.
  32   let CompleteModel = 0;
  33 }
  34
  35 let SchedModel = HaswellModel in {
  36
  37 // Haswell can issue micro-ops to 8 different ports in one cycle.
  38
  39 // Ports 0, 1, 5, and 6 handle all computation.
  40 // Port 4 gets the data half of stores. Store data can be available later than
  41 // the store address, but since we don't model the latency of stores, we can
  42 // ignore that.
  43 // Ports 2 and 3 are identical. They handle loads and the address half of
  44 // stores. Port 7 can handle address calculations.
  45 def HWPort0 : ProcResource<1>;
  46 def HWPort1 : ProcResource<1>;
  47 def HWPort2 : ProcResource<1>;
  48 def HWPort3 : ProcResource<1>;
  49 def HWPort4 : ProcResource<1>;
  50 def HWPort5 : ProcResource<1>;
  51 def HWPort6 : ProcResource<1>;
  52 def HWPort7 : ProcResource<1>;
  53
  54 // Many micro-ops are capable of issuing on multiple ports.
  55 def HWPort01  : ProcResGroup<[HWPort0, HWPort1]>;
  56 def HWPort23  : ProcResGroup<[HWPort2, HWPort3]>;
  57 def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>;
  58 def HWPort04  : ProcResGroup<[HWPort0, HWPort4]>;
  59 def HWPort05  : ProcResGroup<[HWPort0, HWPort5]>;
  60 def HWPort06  : ProcResGroup<[HWPort0, HWPort6]>;
  61 def HWPort15  : ProcResGroup<[HWPort1, HWPort5]>;
  62 def HWPort16  : ProcResGroup<[HWPort1, HWPort6]>;
  63 def HWPort56  : ProcResGroup<[HWPort5, HWPort6]>;
  64 def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>;
  65 def HWPort056 : ProcResGroup<[HWPort0, HWPort5, HWPort6]>;
  66 def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>;
  67
  68 // 60 Entry Unified Scheduler
  69 def HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4,
  70                               HWPort5, HWPort6, HWPort7]> {
  71   let BufferSize=60;
  72 }
  73
  74 // Integer division issued on port 0.
  75 def HWDivider : ProcResource<1>;
  76 // FP division and sqrt on port 0.
  77 def HWFPDivider : ProcResource<1>;
  78
  79 // Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
  80 // cycles after the memory operand.
  81 def : ReadAdvance<ReadAfterLd, 5>;
  82
  83 // Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available
  84 // until 5/6/7 cycles after the memory operand.
  85 def : ReadAdvance<ReadAfterVecLd, 5>;
  86 def : ReadAdvance<ReadAfterVecXLd, 6>;
  87 def : ReadAdvance<ReadAfterVecYLd, 7>;
  88
  89 def : ReadAdvance<ReadInt2Fpu, 0>;
  90
  91 // Many SchedWrites are defined in pairs with and without a folded load.
  92 // Instructions with folded loads are usually micro-fused, so they only appear
  93 // as two micro-ops when queued in the reservation station.
  94 // This multiclass defines the resource usage for variants with and without
  95 // folded loads.
  96 multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,
  97                           list<ProcResourceKind> ExePorts,
  98                           int Lat, list<int> Res = [1], int UOps = 1,
  99                           int LoadLat = 5> {
 100   // Register variant is using a single cycle on ExePort.
 101   def : WriteRes<SchedRW, ExePorts> {
 102     let Latency = Lat;
 103     let ResourceCycles = Res;
 104     let NumMicroOps = UOps;
 105   }
 106
 107   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
 108   // the latency (default = 5).
 109   def : WriteRes<SchedRW.Folded, !listconcat([HWPort23], ExePorts)> {
 110     let Latency = !add(Lat, LoadLat);
 111     let ResourceCycles = !listconcat([1], Res);
 112     let NumMicroOps = !add(UOps, 1);
 113   }
 114 }
 115
 116 // A folded store needs a cycle on port 4 for the store data, and an extra port
 117 // 2/3/7 cycle to recompute the address.
 118 def : WriteRes<WriteRMW, [HWPort237,HWPort4]>;
 119
 120 // Store_addr on 237.
 121 // Store_data on 4.
 122 defm : X86WriteRes<WriteStore,   [HWPort237, HWPort4], 1, [1,1], 1>;
 123 defm : X86WriteRes<WriteStoreNT, [HWPort237, HWPort4], 1, [1,1], 2>;
 124 defm : X86WriteRes<WriteLoad,    [HWPort23], 5, [1], 1>;
 125 defm : X86WriteRes<WriteMove,    [HWPort0156], 1, [1], 1>;
 126 def  : WriteRes<WriteZero,       []>;
 127
 128 // Arithmetic.
 129 defm : HWWriteResPair<WriteALU,    [HWPort0156], 1>;
 130 defm : HWWriteResPair<WriteADC,    [HWPort06, HWPort0156], 2, [1,1], 2>;
 131
 132 // Integer multiplication.
 133 defm : HWWriteResPair<WriteIMul8,     [HWPort1],   3>;
 134 defm : HWWriteResPair<WriteIMul16,    [HWPort1,HWPort06,HWPort0156], 4, [1,1,2], 4>;
 135 defm : X86WriteRes<WriteIMul16Imm,    [HWPort1,HWPort0156], 4, [1,1], 2>;
 136 defm : X86WriteRes<WriteIMul16ImmLd,  [HWPort1,HWPort0156,HWPort23], 8, [1,1,1], 3>;
 137 defm : HWWriteResPair<WriteIMul16Reg, [HWPort1],   3>;
 138 defm : HWWriteResPair<WriteIMul32,    [HWPort1,HWPort06,HWPort0156], 4, [1,1,1], 3>;
 139 defm : HWWriteResPair<WriteIMul32Imm, [HWPort1],   3>;
 140 defm : HWWriteResPair<WriteIMul32Reg, [HWPort1],   3>;
 141 defm : HWWriteResPair<WriteIMul64,    [HWPort1,HWPort6], 4, [1,1], 2>;
 142 defm : HWWriteResPair<WriteIMul64Imm, [HWPort1],   3>;
 143 defm : HWWriteResPair<WriteIMul64Reg, [HWPort1],   3>;
 144 def  : WriteRes<WriteIMulH, []> { let Latency = 3; }
 145
 146 defm : X86WriteRes<WriteBSWAP32,   [HWPort15], 1, [1], 1>;
 147 defm : X86WriteRes<WriteBSWAP64,   [HWPort06, HWPort15], 2, [1,1], 2>;
 148 defm : X86WriteRes<WriteCMPXCHG,[HWPort06, HWPort0156], 5, [2,3], 5>;
 149 defm : X86WriteRes<WriteCMPXCHGRMW,[HWPort23,HWPort06,HWPort0156,HWPort237,HWPort4], 9, [1,2,1,1,1], 6>;
 150 defm : X86WriteRes<WriteXCHG, [HWPort0156], 2, [3], 3>;
 151
 152 // Integer shifts and rotates.
 153 defm : HWWriteResPair<WriteShift,    [HWPort06],  1>;
 154 defm : HWWriteResPair<WriteShiftCL,  [HWPort06, HWPort0156],  3, [2,1], 3>;
 155 defm : HWWriteResPair<WriteRotate,   [HWPort06],  1, [1], 1>;
 156 defm : HWWriteResPair<WriteRotateCL, [HWPort06, HWPort0156],  3, [2,1], 3>;
 157
 158 // SHLD/SHRD.
 159 defm : X86WriteRes<WriteSHDrri, [HWPort1], 3, [1], 1>;
 160 defm : X86WriteRes<WriteSHDrrcl,[HWPort1, HWPort06, HWPort0156], 6, [1, 1, 2], 4>;
 161 defm : X86WriteRes<WriteSHDmri, [HWPort1, HWPort23, HWPort237, HWPort0156], 10, [1, 1, 1, 1], 4>;
 162 defm : X86WriteRes<WriteSHDmrcl,[HWPort1, HWPort23, HWPort237, HWPort06, HWPort0156], 12, [1, 1, 1, 1, 2], 6>;
 163
 164 defm : HWWriteResPair<WriteJump,   [HWPort06],  1>;
 165 defm : HWWriteResPair<WriteCRC32,  [HWPort1],   3>;
 166
 167 defm : HWWriteResPair<WriteCMOV,  [HWPort06,HWPort0156], 2, [1,1], 2>; // Conditional move.
 168 defm : X86WriteRes<WriteFCMOV, [HWPort1], 3, [1], 1>; // x87 conditional move.
 169 def  : WriteRes<WriteSETCC, [HWPort06]>; // Setcc.
 170 def  : WriteRes<WriteSETCCStore, [HWPort06,HWPort4,HWPort237]> {
 171   let Latency = 2;
 172   let NumMicroOps = 3;
 173 }
 174
 175 defm : X86WriteRes<WriteLAHFSAHF,        [HWPort06], 1, [1], 1>;
 176 defm : X86WriteRes<WriteBitTest,         [HWPort06], 1, [1], 1>;
 177 defm : X86WriteRes<WriteBitTestImmLd,    [HWPort06,HWPort23], 6, [1,1], 2>;
 178 defm : X86WriteRes<WriteBitTestRegLd,    [], 1, [], 10>;
 179 defm : X86WriteRes<WriteBitTestSet,      [HWPort06], 1, [1], 1>;
 180 defm : X86WriteRes<WriteBitTestSetImmLd, [HWPort06,HWPort23], 6, [1,1], 3>;
 181 //defm : X86WriteRes<WriteBitTestSetRegLd, [], 1, [], 11>;
 182
 183 // This is for simple LEAs with one or two input operands.
 184 // The complex ones can only execute on port 1, and they require two cycles on
 185 // the port to read all inputs. We don't model that.
 186 def : WriteRes<WriteLEA, [HWPort15]>;
 187
 188 // Bit counts.
 189 defm : HWWriteResPair<WriteBSF, [HWPort1], 3>;
 190 defm : HWWriteResPair<WriteBSR, [HWPort1], 3>;
 191 defm : HWWriteResPair<WriteLZCNT,          [HWPort1], 3>;
 192 defm : HWWriteResPair<WriteTZCNT,          [HWPort1], 3>;
 193 defm : HWWriteResPair<WritePOPCNT,         [HWPort1], 3>;
 194
 195 // BMI1 BEXTR/BLS, BMI2 BZHI
 196 defm : HWWriteResPair<WriteBEXTR, [HWPort06,HWPort15], 2, [1,1], 2>;
 197 defm : HWWriteResPair<WriteBLS,   [HWPort15], 1>;
 198 defm : HWWriteResPair<WriteBZHI,  [HWPort15], 1>;
 199
 200 // TODO: Why isn't the HWDivider used?
 201 defm : X86WriteRes<WriteDiv8,     [HWPort0,HWPort1,HWPort5,HWPort6], 22, [], 9>;
 202 defm : X86WriteRes<WriteDiv16,    [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>;
 203 defm : X86WriteRes<WriteDiv32,    [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>;
 204 defm : X86WriteRes<WriteDiv64,    [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>;
 205 defm : X86WriteRes<WriteDiv8Ld,   [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
 206 defm : X86WriteRes<WriteDiv16Ld,  [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
 207 defm : X86WriteRes<WriteDiv32Ld,  [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
 208 defm : X86WriteRes<WriteDiv64Ld,  [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
 209
 210 defm : X86WriteRes<WriteIDiv8,    [HWPort0,HWPort1,HWPort5,HWPort6], 23, [], 9>;
 211 defm : X86WriteRes<WriteIDiv16,   [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>;
 212 defm : X86WriteRes<WriteIDiv32,   [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>;
 213 defm : X86WriteRes<WriteIDiv64,   [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>;
 214 defm : X86WriteRes<WriteIDiv8Ld,  [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
 215 defm : X86WriteRes<WriteIDiv16Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
 216 defm : X86WriteRes<WriteIDiv32Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
 217 defm : X86WriteRes<WriteIDiv64Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>;
 218
 219 // Scalar and vector floating point.
 220 defm : X86WriteRes<WriteFLD0,          [HWPort01], 1, [1], 1>;
 221 defm : X86WriteRes<WriteFLD1,          [HWPort01], 1, [2], 2>;
 222 defm : X86WriteRes<WriteFLDC,          [HWPort01], 1, [2], 2>;
 223 defm : X86WriteRes<WriteFLoad,         [HWPort23], 5, [1], 1>;
 224 defm : X86WriteRes<WriteFLoadX,        [HWPort23], 6, [1], 1>;
 225 defm : X86WriteRes<WriteFLoadY,        [HWPort23], 7, [1], 1>;
 226 defm : X86WriteRes<WriteFMaskedLoad,   [HWPort23,HWPort5], 8, [1,2], 3>;
 227 defm : X86WriteRes<WriteFMaskedLoadY,  [HWPort23,HWPort5], 9, [1,2], 3>;
 228 defm : X86WriteRes<WriteFStore,        [HWPort237,HWPort4], 1, [1,1], 2>;
 229 defm : X86WriteRes<WriteFStoreX,       [HWPort237,HWPort4], 1, [1,1], 2>;
 230 defm : X86WriteRes<WriteFStoreY,       [HWPort237,HWPort4], 1, [1,1], 2>;
 231 defm : X86WriteRes<WriteFStoreNT,      [HWPort237,HWPort4], 1, [1,1], 2>;
 232 defm : X86WriteRes<WriteFStoreNTX,     [HWPort237,HWPort4], 1, [1,1], 2>;
 233 defm : X86WriteRes<WriteFStoreNTY,     [HWPort237,HWPort4], 1, [1,1], 2>;
 234 defm : X86WriteRes<WriteFMaskedStore,  [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
 235 defm : X86WriteRes<WriteFMaskedStoreY, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
 236 defm : X86WriteRes<WriteFMove,         [HWPort5], 1, [1], 1>;
 237 defm : X86WriteRes<WriteFMoveX,        [HWPort5], 1, [1], 1>;
 238 defm : X86WriteRes<WriteFMoveY,        [HWPort5], 1, [1], 1>;
 239 defm : X86WriteRes<WriteEMMS,          [HWPort01,HWPort15,HWPort015,HWPort0156], 31, [8,1,21,1], 31>;
 240
 241 defm : HWWriteResPair<WriteFAdd,    [HWPort1],  3, [1], 1, 5>;
 242 defm : HWWriteResPair<WriteFAddX,   [HWPort1],  3, [1], 1, 6>;
 243 defm : HWWriteResPair<WriteFAddY,   [HWPort1],  3, [1], 1, 7>;
 244 defm : HWWriteResPair<WriteFAddZ,   [HWPort1],  3, [1], 1, 7>; // Unsupported = 1
 245 defm : HWWriteResPair<WriteFAdd64,  [HWPort1],  3, [1], 1, 5>;
 246 defm : HWWriteResPair<WriteFAdd64X, [HWPort1],  3, [1], 1, 6>;
 247 defm : HWWriteResPair<WriteFAdd64Y, [HWPort1],  3, [1], 1, 7>;
 248 defm : HWWriteResPair<WriteFAdd64Z, [HWPort1],  3, [1], 1, 7>; // Unsupported = 1
 249
 250 defm : HWWriteResPair<WriteFCmp,    [HWPort1],  3, [1], 1, 5>;
 251 defm : HWWriteResPair<WriteFCmpX,   [HWPort1],  3, [1], 1, 6>;
 252 defm : HWWriteResPair<WriteFCmpY,   [HWPort1],  3, [1], 1, 7>;
 253 defm : HWWriteResPair<WriteFCmpZ,   [HWPort1],  3, [1], 1, 7>; // Unsupported = 1
 254 defm : HWWriteResPair<WriteFCmp64,  [HWPort1],  3, [1], 1, 5>;
 255 defm : HWWriteResPair<WriteFCmp64X, [HWPort1],  3, [1], 1, 6>;
 256 defm : HWWriteResPair<WriteFCmp64Y, [HWPort1],  3, [1], 1, 7>;
 257 defm : HWWriteResPair<WriteFCmp64Z, [HWPort1],  3, [1], 1, 7>; // Unsupported = 1
 258
 259 defm : HWWriteResPair<WriteFCom,    [HWPort1],  3>;
 260
 261 defm : HWWriteResPair<WriteFMul,    [HWPort01],  5, [1], 1, 5>;
 262 defm : HWWriteResPair<WriteFMulX,   [HWPort01],  5, [1], 1, 6>;
 263 defm : HWWriteResPair<WriteFMulY,   [HWPort01],  5, [1], 1, 7>;
 264 defm : HWWriteResPair<WriteFMulZ,   [HWPort01],  5, [1], 1, 7>; // Unsupported = 1
 265 defm : HWWriteResPair<WriteFMul64,  [HWPort01],  5, [1], 1, 5>;
 266 defm : HWWriteResPair<WriteFMul64X, [HWPort01],  5, [1], 1, 6>;
 267 defm : HWWriteResPair<WriteFMul64Y, [HWPort01],  5, [1], 1, 7>;
 268 defm : HWWriteResPair<WriteFMul64Z, [HWPort01],  5, [1], 1, 7>; // Unsupported = 1
 269
 270 defm : HWWriteResPair<WriteFDiv,    [HWPort0,HWFPDivider], 13, [1,7], 1, 5>;
 271 defm : HWWriteResPair<WriteFDivX,   [HWPort0,HWFPDivider], 13, [1,7], 1, 6>;
 272 defm : HWWriteResPair<WriteFDivY,   [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>;
 273 defm : HWWriteResPair<WriteFDivZ,   [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; // Unsupported = 1
 274 defm : HWWriteResPair<WriteFDiv64,  [HWPort0,HWFPDivider], 20, [1,14], 1, 5>;
 275 defm : HWWriteResPair<WriteFDiv64X, [HWPort0,HWFPDivider], 20, [1,14], 1, 6>;
 276 defm : HWWriteResPair<WriteFDiv64Y, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>;
 277 defm : HWWriteResPair<WriteFDiv64Z, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; // Unsupported = 1
 278
 279 defm : HWWriteResPair<WriteFRcp,   [HWPort0],  5, [1], 1, 5>;
 280 defm : HWWriteResPair<WriteFRcpX,  [HWPort0],  5, [1], 1, 6>;
 281 defm : HWWriteResPair<WriteFRcpY,  [HWPort0,HWPort015], 11, [2,1], 3, 7>;
 282 defm : HWWriteResPair<WriteFRcpZ,  [HWPort0,HWPort015], 11, [2,1], 3, 7>; // Unsupported = 1
 283
 284 defm : HWWriteResPair<WriteFRsqrt, [HWPort0],  5, [1], 1, 5>;
 285 defm : HWWriteResPair<WriteFRsqrtX,[HWPort0],  5, [1], 1, 6>;
 286 defm : HWWriteResPair<WriteFRsqrtY,[HWPort0,HWPort015], 11, [2,1], 3, 7>;
 287 defm : HWWriteResPair<WriteFRsqrtZ,[HWPort0,HWPort015], 11, [2,1], 3, 7>; // Unsupported = 1
 288
 289 defm : HWWriteResPair<WriteFSqrt,    [HWPort0,HWFPDivider], 11, [1,7], 1, 5>;
 290 defm : HWWriteResPair<WriteFSqrtX,   [HWPort0,HWFPDivider], 11, [1,7], 1, 6>;
 291 defm : HWWriteResPair<WriteFSqrtY,   [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>;
 292 defm : HWWriteResPair<WriteFSqrtZ,   [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; // Unsupported = 1
 293 defm : HWWriteResPair<WriteFSqrt64,  [HWPort0,HWFPDivider], 16, [1,14], 1, 5>;
 294 defm : HWWriteResPair<WriteFSqrt64X, [HWPort0,HWFPDivider], 16, [1,14], 1, 6>;
 295 defm : HWWriteResPair<WriteFSqrt64Y, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>;
 296 defm : HWWriteResPair<WriteFSqrt64Z, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; // Unsupported = 1
 297 defm : HWWriteResPair<WriteFSqrt80,  [HWPort0,HWFPDivider], 23, [1,17]>;
 298
 299 defm : HWWriteResPair<WriteFMA,   [HWPort01], 5, [1], 1, 5>;
 300 defm : HWWriteResPair<WriteFMAX,  [HWPort01], 5, [1], 1, 6>;
 301 defm : HWWriteResPair<WriteFMAY,  [HWPort01], 5, [1], 1, 7>;
 302 defm : HWWriteResPair<WriteFMAZ,  [HWPort01], 5, [1], 1, 7>; // Unsupported = 1
 303 defm : HWWriteResPair<WriteDPPD,  [HWPort0,HWPort1,HWPort5],  9, [1,1,1], 3, 6>;
 304 defm : HWWriteResPair<WriteDPPS,  [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 6>;
 305 defm : HWWriteResPair<WriteDPPSY, [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 7>;
 306 defm : HWWriteResPair<WriteDPPSZ, [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 7>; // Unsupported = 1
 307 defm : HWWriteResPair<WriteFSign,  [HWPort0], 1>;
 308 defm : X86WriteRes<WriteFRnd,            [HWPort23],  6, [1],   1>;
 309 defm : X86WriteRes<WriteFRndY,           [HWPort23],  6, [1],   1>;
 310 defm : X86WriteRes<WriteFRndZ,           [HWPort23],  6, [1],   1>; // Unsupported = 1
 311 defm : X86WriteRes<WriteFRndLd,  [HWPort1,HWPort23], 12, [2,1], 3>;
 312 defm : X86WriteRes<WriteFRndYLd, [HWPort1,HWPort23], 13, [2,1], 3>;
 313 defm : X86WriteRes<WriteFRndZLd, [HWPort1,HWPort23], 13, [2,1], 3>; // Unsupported = 1
 314 defm : HWWriteResPair<WriteFLogic,  [HWPort5], 1, [1], 1, 6>;
 315 defm : HWWriteResPair<WriteFLogicY, [HWPort5], 1, [1], 1, 7>;
 316 defm : HWWriteResPair<WriteFLogicZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1
 317 defm : HWWriteResPair<WriteFTest,   [HWPort0], 1, [1], 1, 6>;
 318 defm : HWWriteResPair<WriteFTestY,  [HWPort0], 1, [1], 1, 7>;
 319 defm : HWWriteResPair<WriteFTestZ,  [HWPort0], 1, [1], 1, 7>; // Unsupported = 1
 320 defm : HWWriteResPair<WriteFShuffle,  [HWPort5], 1, [1], 1, 6>;
 321 defm : HWWriteResPair<WriteFShuffleY, [HWPort5], 1, [1], 1, 7>;
 322 defm : HWWriteResPair<WriteFShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1
 323 defm : HWWriteResPair<WriteFVarShuffle,  [HWPort5], 1, [1], 1, 6>;
 324 defm : HWWriteResPair<WriteFVarShuffleY, [HWPort5], 1, [1], 1, 7>;
 325 defm : HWWriteResPair<WriteFVarShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1
 326 defm : HWWriteResPair<WriteFBlend,  [HWPort015], 1, [1], 1, 6>;
 327 defm : HWWriteResPair<WriteFBlendY, [HWPort015], 1, [1], 1, 7>;
 328 defm : HWWriteResPair<WriteFBlendZ, [HWPort015], 1, [1], 1, 7>; // Unsupported = 1
 329 defm : HWWriteResPair<WriteFShuffle256, [HWPort5], 3, [1], 1, 7>;
 330 defm : HWWriteResPair<WriteFVarShuffle256, [HWPort5], 3, [1], 1, 7>;
 331 defm : HWWriteResPair<WriteFVarBlend,  [HWPort5], 2, [2], 2, 6>;
 332 defm : HWWriteResPair<WriteFVarBlendY, [HWPort5], 2, [2], 2, 7>;
 333 defm : HWWriteResPair<WriteFVarBlendZ, [HWPort5], 2, [2], 2, 7>; // Unsupported = 1
 334
 335 // Conversion between integer and float.
 336 defm : HWWriteResPair<WriteCvtSD2I,   [HWPort1], 3>;
 337 defm : HWWriteResPair<WriteCvtPD2I,   [HWPort1], 3>;
 338 defm : HWWriteResPair<WriteCvtPD2IY,  [HWPort1], 3>;
 339 defm : HWWriteResPair<WriteCvtPD2IZ,  [HWPort1], 3>; // Unsupported = 1
 340 defm : HWWriteResPair<WriteCvtSS2I,   [HWPort1], 3>;
 341 defm : HWWriteResPair<WriteCvtPS2I,   [HWPort1], 3>;
 342 defm : HWWriteResPair<WriteCvtPS2IY,  [HWPort1], 3>;
 343 defm : HWWriteResPair<WriteCvtPS2IZ,  [HWPort1], 3>; // Unsupported = 1
 344
 345 defm : HWWriteResPair<WriteCvtI2SD,   [HWPort1], 4>;
 346 defm : HWWriteResPair<WriteCvtI2PD,   [HWPort1], 4>;
 347 defm : HWWriteResPair<WriteCvtI2PDY,  [HWPort1], 4>;
 348 defm : HWWriteResPair<WriteCvtI2PDZ,  [HWPort1], 4>; // Unsupported = 1
 349 defm : HWWriteResPair<WriteCvtI2SS,   [HWPort1], 4>;
 350 defm : HWWriteResPair<WriteCvtI2PS,   [HWPort1], 4>;
 351 defm : HWWriteResPair<WriteCvtI2PSY,  [HWPort1], 4>;
 352 defm : HWWriteResPair<WriteCvtI2PSZ,  [HWPort1], 4>; // Unsupported = 1
 353
 354 defm : HWWriteResPair<WriteCvtSS2SD,  [HWPort1], 3>;
 355 defm : HWWriteResPair<WriteCvtPS2PD,  [HWPort1], 3>;
 356 defm : HWWriteResPair<WriteCvtPS2PDY, [HWPort1], 3>;
 357 defm : HWWriteResPair<WriteCvtPS2PDZ, [HWPort1], 3>; // Unsupported = 1
 358 defm : HWWriteResPair<WriteCvtSD2SS,  [HWPort1], 3>;
 359 defm : HWWriteResPair<WriteCvtPD2PS,  [HWPort1], 3>;
 360 defm : HWWriteResPair<WriteCvtPD2PSY, [HWPort1], 3>;
 361 defm : HWWriteResPair<WriteCvtPD2PSZ, [HWPort1], 3>; // Unsupported = 1
 362
 363 defm : X86WriteRes<WriteCvtPH2PS,     [HWPort0,HWPort5], 2, [1,1], 2>;
 364 defm : X86WriteRes<WriteCvtPH2PSY,    [HWPort0,HWPort5], 2, [1,1], 2>;
 365 defm : X86WriteRes<WriteCvtPH2PSZ,    [HWPort0,HWPort5], 2, [1,1], 2>; // Unsupported = 1
 366 defm : X86WriteRes<WriteCvtPH2PSLd,  [HWPort0,HWPort23], 6, [1,1], 2>;
 367 defm : X86WriteRes<WriteCvtPH2PSYLd, [HWPort0,HWPort23], 7, [1,1], 2>;
 368 defm : X86WriteRes<WriteCvtPH2PSZLd, [HWPort0,HWPort23], 7, [1,1], 2>; // Unsupported = 1
 369
 370 defm : X86WriteRes<WriteCvtPS2PH,    [HWPort1,HWPort5], 4, [1,1], 2>;
 371 defm : X86WriteRes<WriteCvtPS2PHY,   [HWPort1,HWPort5], 6, [1,1], 2>;
 372 defm : X86WriteRes<WriteCvtPS2PHZ,   [HWPort1,HWPort5], 6, [1,1], 2>; // Unsupported = 1
 373 defm : X86WriteRes<WriteCvtPS2PHSt,  [HWPort1,HWPort4,HWPort5,HWPort237], 5, [1,1,1,1], 4>;
 374 defm : X86WriteRes<WriteCvtPS2PHYSt, [HWPort1,HWPort4,HWPort5,HWPort237], 7, [1,1,1,1], 4>;
 375 defm : X86WriteRes<WriteCvtPS2PHZSt, [HWPort1,HWPort4,HWPort5,HWPort237], 7, [1,1,1,1], 4>; // Unsupported = 1
 376
 377 // Vector integer operations.
 378 defm : X86WriteRes<WriteVecLoad,         [HWPort23], 5, [1], 1>;
 379 defm : X86WriteRes<WriteVecLoadX,        [HWPort23], 6, [1], 1>;
 380 defm : X86WriteRes<WriteVecLoadY,        [HWPort23], 7, [1], 1>;
 381 defm : X86WriteRes<WriteVecLoadNT,       [HWPort23], 6, [1], 1>;
 382 defm : X86WriteRes<WriteVecLoadNTY,      [HWPort23], 7, [1], 1>;
 383 defm : X86WriteRes<WriteVecMaskedLoad,   [HWPort23,HWPort5], 8, [1,2], 3>;
 384 defm : X86WriteRes<WriteVecMaskedLoadY,  [HWPort23,HWPort5], 9, [1,2], 3>;
 385 defm : X86WriteRes<WriteVecStore,        [HWPort237,HWPort4], 1, [1,1], 2>;
 386 defm : X86WriteRes<WriteVecStoreX,       [HWPort237,HWPort4], 1, [1,1], 2>;
 387 defm : X86WriteRes<WriteVecStoreY,       [HWPort237,HWPort4], 1, [1,1], 2>;
 388 defm : X86WriteRes<WriteVecStoreNT,      [HWPort237,HWPort4], 1, [1,1], 2>;
 389 defm : X86WriteRes<WriteVecStoreNTY,     [HWPort237,HWPort4], 1, [1,1], 2>;
 390 defm : X86WriteRes<WriteVecMaskedStore,  [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
 391 defm : X86WriteRes<WriteVecMaskedStoreY, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>;
 392 defm : X86WriteRes<WriteVecMove,         [HWPort015], 1, [1], 1>;
 393 defm : X86WriteRes<WriteVecMoveX,        [HWPort015], 1, [1], 1>;
 394 defm : X86WriteRes<WriteVecMoveY,        [HWPort015], 1, [1], 1>;
 395 defm : X86WriteRes<WriteVecMoveToGpr,    [HWPort0], 1, [1], 1>;
 396 defm : X86WriteRes<WriteVecMoveFromGpr,  [HWPort5], 1, [1], 1>;
 397
 398 defm : HWWriteResPair<WriteVecLogic, [HWPort015], 1, [1], 1, 5>;
 399 defm : HWWriteResPair<WriteVecLogicX,[HWPort015], 1, [1], 1, 6>;
 400 defm : HWWriteResPair<WriteVecLogicY,[HWPort015], 1, [1], 1, 7>;
 401 defm : HWWriteResPair<WriteVecLogicZ,[HWPort015], 1, [1], 1, 7>; // Unsupported = 1
 402 defm : HWWriteResPair<WriteVecTest,  [HWPort0,HWPort5], 2, [1,1], 2, 6>;
 403 defm : HWWriteResPair<WriteVecTestY, [HWPort0,HWPort5], 4, [1,1], 2, 7>;
 404 defm : HWWriteResPair<WriteVecTestZ, [HWPort0,HWPort5], 4, [1,1], 2, 7>; // Unsupported = 1
 405 defm : HWWriteResPair<WriteVecALU,   [HWPort15],  1, [1], 1, 5>;
 406 defm : HWWriteResPair<WriteVecALUX,  [HWPort15],  1, [1], 1, 6>;
 407 defm : HWWriteResPair<WriteVecALUY,  [HWPort15],  1, [1], 1, 7>;
 408 defm : HWWriteResPair<WriteVecALUZ,  [HWPort15],  1, [1], 1, 7>; // Unsupported = 1
 409 defm : HWWriteResPair<WriteVecIMul,  [HWPort0],  5, [1], 1, 5>;
 410 defm : HWWriteResPair<WriteVecIMulX, [HWPort0],  5, [1], 1, 6>;
 411 defm : HWWriteResPair<WriteVecIMulY, [HWPort0],  5, [1], 1, 7>;
 412 defm : HWWriteResPair<WriteVecIMulZ, [HWPort0],  5, [1], 1, 7>; // Unsupported = 1
 413 defm : HWWriteResPair<WritePMULLD,   [HWPort0], 10, [2], 2, 6>;
 414 defm : HWWriteResPair<WritePMULLDY,  [HWPort0], 10, [2], 2, 7>;
 415 defm : HWWriteResPair<WritePMULLDZ,  [HWPort0], 10, [2], 2, 7>; // Unsupported = 1
 416 defm : HWWriteResPair<WriteShuffle,  [HWPort5],  1, [1], 1, 5>;
 417 defm : HWWriteResPair<WriteShuffleX, [HWPort5],  1, [1], 1, 6>;
 418 defm : HWWriteResPair<WriteShuffleY, [HWPort5],  1, [1], 1, 7>;
 419 defm : HWWriteResPair<WriteShuffleZ, [HWPort5],  1, [1], 1, 7>; // Unsupported = 1
 420 defm : HWWriteResPair<WriteVarShuffle, [HWPort5], 1, [1], 1, 5>;
 421 defm : HWWriteResPair<WriteVarShuffleX,[HWPort5], 1, [1], 1, 6>;
 422 defm : HWWriteResPair<WriteVarShuffleY,[HWPort5], 1, [1], 1, 7>;
 423 defm : HWWriteResPair<WriteVarShuffleZ,[HWPort5], 1, [1], 1, 7>; // Unsupported = 1
 424 defm : HWWriteResPair<WriteBlend,  [HWPort5], 1, [1], 1, 6>;
 425 defm : HWWriteResPair<WriteBlendY, [HWPort5], 1, [1], 1, 7>;
 426 defm : HWWriteResPair<WriteBlendZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1
 427 defm : HWWriteResPair<WriteShuffle256, [HWPort5], 3, [1], 1, 7>;
 428 defm : HWWriteResPair<WriteVarShuffle256, [HWPort5], 3, [1], 1, 7>;
 429 defm : HWWriteResPair<WriteVarBlend,  [HWPort5], 2, [2], 2, 6>;
 430 defm : HWWriteResPair<WriteVarBlendY, [HWPort5], 2, [2], 2, 7>;
 431 defm : HWWriteResPair<WriteVarBlendZ, [HWPort5], 2, [2], 2, 7>; // Unsupported = 1
 432 defm : HWWriteResPair<WriteMPSAD,  [HWPort0, HWPort5], 7, [1, 2], 3, 6>;
 433 defm : HWWriteResPair<WriteMPSADY, [HWPort0, HWPort5], 7, [1, 2], 3, 7>;
 434 defm : HWWriteResPair<WriteMPSADZ, [HWPort0, HWPort5], 7, [1, 2], 3, 7>; // Unsupported = 1
 435 defm : HWWriteResPair<WritePSADBW,  [HWPort0], 5, [1], 1, 5>;
 436 defm : HWWriteResPair<WritePSADBWX, [HWPort0], 5, [1], 1, 6>;
 437 defm : HWWriteResPair<WritePSADBWY, [HWPort0], 5, [1], 1, 7>;
 438 defm : HWWriteResPair<WritePSADBWZ, [HWPort0], 5, [1], 1, 7>; // Unsupported = 1
 439 defm : HWWriteResPair<WritePHMINPOS, [HWPort0],  5, [1], 1, 6>;
 440
 441 // Vector integer shifts.
 442 defm : HWWriteResPair<WriteVecShift,     [HWPort0], 1, [1], 1, 5>;
 443 defm : HWWriteResPair<WriteVecShiftX,    [HWPort0,HWPort5],  2, [1,1], 2, 6>;
 444 defm : X86WriteRes<WriteVecShiftY,       [HWPort0,HWPort5],  4, [1,1], 2>;
 445 defm : X86WriteRes<WriteVecShiftZ,       [HWPort0,HWPort5],  4, [1,1], 2>; // Unsupported = 1
 446 defm : X86WriteRes<WriteVecShiftYLd,     [HWPort0,HWPort23], 8, [1,1], 2>;
 447 defm : X86WriteRes<WriteVecShiftZLd,     [HWPort0,HWPort23], 8, [1,1], 2>; // Unsupported = 1
 448
 449 defm : HWWriteResPair<WriteVecShiftImm,  [HWPort0], 1, [1], 1, 5>;
 450 defm : HWWriteResPair<WriteVecShiftImmX, [HWPort0], 1, [1], 1, 6>;
 451 defm : HWWriteResPair<WriteVecShiftImmY, [HWPort0], 1, [1], 1, 7>;
 452 defm : HWWriteResPair<WriteVecShiftImmZ, [HWPort0], 1, [1], 1, 7>; // Unsupported = 1
 453 defm : HWWriteResPair<WriteVarVecShift,  [HWPort0, HWPort5], 3, [2,1], 3, 6>;
 454 defm : HWWriteResPair<WriteVarVecShiftY, [HWPort0, HWPort5], 3, [2,1], 3, 7>;
 455 defm : HWWriteResPair<WriteVarVecShiftZ, [HWPort0, HWPort5], 3, [2,1], 3, 7>; // Unsupported = 1
 456
 457 // Vector insert/extract operations.
 458 def : WriteRes<WriteVecInsert, [HWPort5]> {
 459   let Latency = 2;
 460   let NumMicroOps = 2;
 461   let ResourceCycles = [2];
 462 }
 463 def : WriteRes<WriteVecInsertLd, [HWPort5,HWPort23]> {
 464   let Latency = 6;
 465   let NumMicroOps = 2;
 466 }
 467 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
 468
 469 def : WriteRes<WriteVecExtract, [HWPort0,HWPort5]> {
 470   let Latency = 2;
 471   let NumMicroOps = 2;
 472 }
 473 def : WriteRes<WriteVecExtractSt, [HWPort4,HWPort5,HWPort237]> {
 474   let Latency = 2;
 475   let NumMicroOps = 3;
 476 }
 477
 478 // String instructions.
 479
 480 // Packed Compare Implicit Length Strings, Return Mask
 481 def : WriteRes<WritePCmpIStrM, [HWPort0]> {
 482   let Latency = 11;
 483   let NumMicroOps = 3;
 484   let ResourceCycles = [3];
 485 }
 486 def : WriteRes<WritePCmpIStrMLd, [HWPort0, HWPort23]> {
 487   let Latency = 17;
 488   let NumMicroOps = 4;
 489   let ResourceCycles = [3,1];
 490 }
 491
 492 // Packed Compare Explicit Length Strings, Return Mask
 493 def : WriteRes<WritePCmpEStrM, [HWPort0, HWPort5, HWPort015, HWPort0156]> {
 494   let Latency = 19;
 495   let NumMicroOps = 9;
 496   let ResourceCycles = [4,3,1,1];
 497 }
 498 def : WriteRes<WritePCmpEStrMLd, [HWPort0, HWPort5, HWPort23, HWPort015, HWPort0156]> {
 499   let Latency = 25;
 500   let NumMicroOps = 10;
 501   let ResourceCycles = [4,3,1,1,1];
 502 }
 503
 504 // Packed Compare Implicit Length Strings, Return Index
 505 def : WriteRes<WritePCmpIStrI, [HWPort0]> {
 506   let Latency = 11;
 507   let NumMicroOps = 3;
 508   let ResourceCycles = [3];
 509 }
 510 def : WriteRes<WritePCmpIStrILd, [HWPort0, HWPort23]> {
 511   let Latency = 17;
 512   let NumMicroOps = 4;
 513   let ResourceCycles = [3,1];
 514 }
 515
 516 // Packed Compare Explicit Length Strings, Return Index
 517 def : WriteRes<WritePCmpEStrI, [HWPort0, HWPort5, HWPort0156]> {
 518   let Latency = 18;
 519   let NumMicroOps = 8;
 520   let ResourceCycles = [4,3,1];
 521 }
 522 def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort5, HWPort23, HWPort0156]> {
 523   let Latency = 24;
 524   let NumMicroOps = 9;
 525   let ResourceCycles = [4,3,1,1];
 526 }
 527
 528 // MOVMSK Instructions.
 529 def : WriteRes<WriteFMOVMSK,    [HWPort0]> { let Latency = 3; }
 530 def : WriteRes<WriteVecMOVMSK,  [HWPort0]> { let Latency = 3; }
 531 def : WriteRes<WriteVecMOVMSKY, [HWPort0]> { let Latency = 3; }
 532 def : WriteRes<WriteMMXMOVMSK,  [HWPort0]> { let Latency = 1; }
 533
 534 // AES Instructions.
 535 def : WriteRes<WriteAESDecEnc, [HWPort5]> {
 536   let Latency = 7;
 537   let NumMicroOps = 1;
 538   let ResourceCycles = [1];
 539 }
 540 def : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> {
 541   let Latency = 13;
 542   let NumMicroOps = 2;
 543   let ResourceCycles = [1,1];
 544 }
 545
 546 def : WriteRes<WriteAESIMC, [HWPort5]> {
 547   let Latency = 14;
 548   let NumMicroOps = 2;
 549   let ResourceCycles = [2];
 550 }
 551 def : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> {
 552   let Latency = 20;
 553   let NumMicroOps = 3;
 554   let ResourceCycles = [2,1];
 555 }
 556
 557 def : WriteRes<WriteAESKeyGen, [HWPort0,HWPort5,HWPort015]> {
 558   let Latency = 29;
 559   let NumMicroOps = 11;
 560   let ResourceCycles = [2,7,2];
 561 }
 562 def : WriteRes<WriteAESKeyGenLd, [HWPort0,HWPort5,HWPort23,HWPort015]> {
 563   let Latency = 34;
 564   let NumMicroOps = 11;
 565   let ResourceCycles = [2,7,1,1];
 566 }
 567
 568 // Carry-less multiplication instructions.
 569 def : WriteRes<WriteCLMul, [HWPort0, HWPort5]> {
 570   let Latency = 11;
 571   let NumMicroOps = 3;
 572   let ResourceCycles = [2,1];
 573 }
 574 def : WriteRes<WriteCLMulLd, [HWPort0, HWPort5, HWPort23]> {
 575   let Latency = 17;
 576   let NumMicroOps = 4;
 577   let ResourceCycles = [2,1,1];
 578 }
 579
 580 // Load/store MXCSR.
 581 def : WriteRes<WriteLDMXCSR, [HWPort0,HWPort23,HWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 582 def : WriteRes<WriteSTMXCSR, [HWPort4,HWPort5,HWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 583
 584 def : WriteRes<WriteSystem,     [HWPort0156]> { let Latency = 100; }
 585 def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; }
 586 def : WriteRes<WriteFence,  [HWPort23, HWPort4]>;
 587 def : WriteRes<WriteNop, []>;
 588
 589 //================ Exceptions ================//
 590
 591 //-- Specific Scheduling Models --//
 592
 593 // Starting with P0.
 594 def HWWriteP0 : SchedWriteRes<[HWPort0]>;
 595
 596 def HWWriteP01 : SchedWriteRes<[HWPort01]>;
 597
 598 def HWWrite2P01 : SchedWriteRes<[HWPort01]> {
 599   let NumMicroOps = 2;
 600 }
 601 def HWWrite3P01 : SchedWriteRes<[HWPort01]> {
 602   let NumMicroOps = 3;
 603 }
 604
 605 def HWWriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
 606   let NumMicroOps = 2;
 607 }
 608
 609 def HWWrite2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
 610   let NumMicroOps = 3;
 611   let ResourceCycles = [2, 1];
 612 }
 613
 614 // Starting with P1.
 615 def HWWriteP1 : SchedWriteRes<[HWPort1]>;
 616
 617
 618 def HWWrite2P1 : SchedWriteRes<[HWPort1]> {
 619   let NumMicroOps = 2;
 620   let ResourceCycles = [2];
 621 }
 622
 623 // Notation:
 624 // - r: register.
 625 // - mm: 64 bit mmx register.
 626 // - x = 128 bit xmm register.
 627 // - (x)mm = mmx or xmm register.
 628 // - y = 256 bit ymm register.
 629 // - v = any vector register.
 630 // - m = memory.
 631
 632 //=== Integer Instructions ===//
 633 //-- Move instructions --//
 634
 635 // XLAT.
 636 def HWWriteXLAT : SchedWriteRes<[]> {
 637   let Latency = 7;
 638   let NumMicroOps = 3;
 639 }
 640 def : InstRW<[HWWriteXLAT], (instrs XLAT)>;
 641
 642 // PUSHA.
 643 def HWWritePushA : SchedWriteRes<[]> {
 644   let NumMicroOps = 19;
 645 }
 646 def : InstRW<[HWWritePushA], (instregex "PUSHA(16|32)")>;
 647
 648 // POPA.
 649 def HWWritePopA : SchedWriteRes<[]> {
 650   let NumMicroOps = 18;
 651 }
 652 def : InstRW<[HWWritePopA], (instregex "POPA(16|32)")>;
 653
 654 //-- Arithmetic instructions --//
 655
 656 // BTR BTS BTC.
 657 // m,r.
 658 def HWWriteBTRSCmr : SchedWriteRes<[]> {
 659   let NumMicroOps = 11;
 660 }
 661 def : SchedAlias<WriteBitTestSetRegRMW, HWWriteBTRSCmr>;
 662
 663 //-- Control transfer instructions --//
 664
 665 // CALL.
 666 // i.
 667 def HWWriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> {
 668   let NumMicroOps = 4;
 669   let ResourceCycles = [1, 2, 1];
 670 }
 671 def : InstRW<[HWWriteRETI], (instregex "RETI(L|Q|W)", "LRETI(L|Q|W)")>;
 672
 673 // BOUND.
 674 // r,m.
 675 def HWWriteBOUND : SchedWriteRes<[]> {
 676   let NumMicroOps = 15;
 677 }
 678 def : InstRW<[HWWriteBOUND], (instregex "BOUNDS(16|32)rm")>;
 679
 680 // INTO.
 681 def HWWriteINTO : SchedWriteRes<[]> {
 682   let NumMicroOps = 4;
 683 }
 684 def : InstRW<[HWWriteINTO], (instrs INTO)>;
 685
 686 //-- String instructions --//
 687
 688 // LODSB/W.
 689 def : InstRW<[HWWrite2P0156_P23], (instregex "LODS(B|W)")>;
 690
 691 // LODSD/Q.
 692 def : InstRW<[HWWriteP0156_P23], (instregex "LODS(L|Q)")>;
 693
 694 // MOVS.
 695 def HWWriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> {
 696   let Latency = 4;
 697   let NumMicroOps = 5;
 698   let ResourceCycles = [2, 1, 2];
 699 }
 700 def : InstRW<[HWWriteMOVS], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>;
 701
 702 // CMPS.
 703 def HWWriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> {
 704   let Latency = 4;
 705   let NumMicroOps = 5;
 706   let ResourceCycles = [2, 3];
 707 }
 708 def : InstRW<[HWWriteCMPS], (instregex "CMPS(B|L|Q|W)")>;
 709
 710 //-- Other --//
 711
 712 // RDPMC.f
 713 def HWWriteRDPMC : SchedWriteRes<[]> {
 714   let NumMicroOps = 34;
 715 }
 716 def : InstRW<[HWWriteRDPMC], (instrs RDPMC)>;
 717
 718 // RDRAND.
 719 def HWWriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> {
 720   let NumMicroOps = 17;
 721   let ResourceCycles = [1, 16];
 722 }
 723 def : InstRW<[HWWriteRDRAND], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>;
 724
 725 //=== Floating Point x87 Instructions ===//
 726 //-- Move instructions --//
 727
 728 // FLD.
 729 // m80.
 730 def : InstRW<[HWWriteP01], (instrs LD_Frr)>;
 731
 732 // FBLD.
 733 // m80.
 734 def HWWriteFBLD : SchedWriteRes<[]> {
 735   let Latency = 47;
 736   let NumMicroOps = 43;
 737 }
 738 def : InstRW<[HWWriteFBLD], (instrs FBLDm)>;
 739
 740 // FST(P).
 741 // r.
 742 def : InstRW<[HWWriteP01], (instregex "ST_(F|FP)rr")>;
 743
 744 // FFREE.
 745 def : InstRW<[HWWriteP01], (instregex "FFREE")>;
 746
 747 // FNSAVE.
 748 def HWWriteFNSAVE : SchedWriteRes<[]> {
 749   let NumMicroOps = 147;
 750 }
 751 def : InstRW<[HWWriteFNSAVE], (instrs FSAVEm)>;
 752
 753 // FRSTOR.
 754 def HWWriteFRSTOR : SchedWriteRes<[]> {
 755   let NumMicroOps = 90;
 756 }
 757 def : InstRW<[HWWriteFRSTOR], (instrs FRSTORm)>;
 758
 759 //-- Arithmetic instructions --//
 760
 761 // FCOMPP FUCOMPP.
 762 // r.
 763 def : InstRW<[HWWrite2P01], (instrs FCOMPP, UCOM_FPPr)>;
 764
 765 // FCOMI(P) FUCOMI(P).
 766 // m.
 767 def : InstRW<[HWWrite3P01], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>;
 768
 769 // FTST.
 770 def : InstRW<[HWWriteP1], (instregex "TST_F")>;
 771
 772 // FXAM.
 773 def : InstRW<[HWWrite2P1], (instrs FXAM)>;
 774
 775 // FPREM.
 776 def HWWriteFPREM : SchedWriteRes<[]> {
 777   let Latency = 19;
 778   let NumMicroOps = 28;
 779 }
 780 def : InstRW<[HWWriteFPREM], (instrs FPREM)>;
 781
 782 // FPREM1.
 783 def HWWriteFPREM1 : SchedWriteRes<[]> {
 784   let Latency = 27;
 785   let NumMicroOps = 41;
 786 }
 787 def : InstRW<[HWWriteFPREM1], (instrs FPREM1)>;
 788
 789 // FRNDINT.
 790 def HWWriteFRNDINT : SchedWriteRes<[]> {
 791   let Latency = 11;
 792   let NumMicroOps = 17;
 793 }
 794 def : InstRW<[HWWriteFRNDINT], (instrs FRNDINT)>;
 795
 796 //-- Math instructions --//
 797
 798 // FSCALE.
 799 def HWWriteFSCALE : SchedWriteRes<[]> {
 800   let Latency = 75; // 49-125
 801   let NumMicroOps = 50; // 25-75
 802 }
 803 def : InstRW<[HWWriteFSCALE], (instrs FSCALE)>;
 804
 805 // FXTRACT.
 806 def HWWriteFXTRACT : SchedWriteRes<[]> {
 807   let Latency = 15;
 808   let NumMicroOps = 17;
 809 }
 810 def : InstRW<[HWWriteFXTRACT], (instrs FXTRACT)>;
 811
 812 ////////////////////////////////////////////////////////////////////////////////
 813 // Horizontal add/sub  instructions.
 814 ////////////////////////////////////////////////////////////////////////////////
 815
 816 defm : HWWriteResPair<WriteFHAdd,  [HWPort1, HWPort5], 5, [1,2], 3, 6>;
 817 defm : HWWriteResPair<WriteFHAddY, [HWPort1, HWPort5], 5, [1,2], 3, 7>;
 818 defm : HWWriteResPair<WritePHAdd,  [HWPort5, HWPort15], 3, [2,1], 3, 5>;
 819 defm : HWWriteResPair<WritePHAddX, [HWPort5, HWPort15], 3, [2,1], 3, 6>;
 820 defm : HWWriteResPair<WritePHAddY, [HWPort5, HWPort15], 3, [2,1], 3, 7>;
 821
 822 //=== Floating Point XMM and YMM Instructions ===//
 823
 824 // Remaining instrs.
 825
 826 def HWWriteResGroup0 : SchedWriteRes<[HWPort23]> {
 827   let Latency = 6;
 828   let NumMicroOps = 1;
 829   let ResourceCycles = [1];
 830 }
 831 def: InstRW<[HWWriteResGroup0], (instrs VBROADCASTSSrm)>;
 832 def: InstRW<[HWWriteResGroup0], (instregex "(V?)MOVSHDUPrm",
 833                                            "(V?)MOVSLDUPrm",
 834                                            "VPBROADCAST(D|Q)rm")>;
 835
 836 def HWWriteResGroup0_1 : SchedWriteRes<[HWPort23]> {
 837   let Latency = 7;
 838   let NumMicroOps = 1;
 839   let ResourceCycles = [1];
 840 }
 841 def: InstRW<[HWWriteResGroup0_1], (instrs VBROADCASTF128,
 842                                           VBROADCASTI128,
 843                                           VBROADCASTSDYrm,
 844                                           VBROADCASTSSYrm,
 845                                           VMOVDDUPYrm,
 846                                           VMOVSHDUPYrm,
 847                                           VMOVSLDUPYrm)>;
 848 def: InstRW<[HWWriteResGroup0_1], (instregex "LD_F(32|64|80)m",
 849                                              "VPBROADCAST(D|Q)Yrm")>;
 850
 851 def HWWriteResGroup0_2 : SchedWriteRes<[HWPort23]> {
 852   let Latency = 5;
 853   let NumMicroOps = 1;
 854   let ResourceCycles = [1];
 855 }
 856 def: InstRW<[HWWriteResGroup0_2], (instregex "MOVSX(16|32|64)rm(8|16|32)",
 857                                              "MOVZX(16|32|64)rm(8|16)",
 858                                              "(V?)MOVDDUPrm")>;
 859
 860 def HWWriteResGroup1 : SchedWriteRes<[HWPort4,HWPort237]> {
 861   let Latency = 1;
 862   let NumMicroOps = 2;
 863   let ResourceCycles = [1,1];
 864 }
 865 def: InstRW<[HWWriteResGroup1], (instrs FBSTPm, VMPTRSTm)>;
 866 def: InstRW<[HWWriteResGroup1], (instregex "ST_FP(32|64|80)m")>;
 867
 868 def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> {
 869   let Latency = 1;
 870   let NumMicroOps = 1;
 871   let ResourceCycles = [1];
 872 }
 873 def: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQ(Y?)rr",
 874                                            "VPSRLVQ(Y?)rr")>;
 875
 876 def HWWriteResGroup3 : SchedWriteRes<[HWPort1]> {
 877   let Latency = 1;
 878   let NumMicroOps = 1;
 879   let ResourceCycles = [1];
 880 }
 881 def: InstRW<[HWWriteResGroup3], (instregex "COM(P?)_FST0r",
 882                                            "UCOM_F(P?)r")>;
 883
 884 def HWWriteResGroup4 : SchedWriteRes<[HWPort5]> {
 885   let Latency = 1;
 886   let NumMicroOps = 1;
 887   let ResourceCycles = [1];
 888 }
 889 def: InstRW<[HWWriteResGroup4], (instrs MMX_MOVQ2DQrr)>;
 890
 891 def HWWriteResGroup5 : SchedWriteRes<[HWPort6]> {
 892   let Latency = 1;
 893   let NumMicroOps = 1;
 894   let ResourceCycles = [1];
 895 }
 896 def: InstRW<[HWWriteResGroup5], (instregex "JMP(16|32|64)r")>;
 897
 898 def HWWriteResGroup6 : SchedWriteRes<[HWPort01]> {
 899   let Latency = 1;
 900   let NumMicroOps = 1;
 901   let ResourceCycles = [1];
 902 }
 903 def: InstRW<[HWWriteResGroup6], (instrs FINCSTP, FNOP)>;
 904
 905 def HWWriteResGroup7 : SchedWriteRes<[HWPort06]> {
 906   let Latency = 1;
 907   let NumMicroOps = 1;
 908   let ResourceCycles = [1];
 909 }
 910 def: InstRW<[HWWriteResGroup7], (instrs CDQ, CQO)>;
 911
 912 def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> {
 913   let Latency = 1;
 914   let NumMicroOps = 1;
 915   let ResourceCycles = [1];
 916 }
 917 def: InstRW<[HWWriteResGroup8], (instregex "ANDN(32|64)rr")>;
 918
 919 def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> {
 920   let Latency = 1;
 921   let NumMicroOps = 1;
 922   let ResourceCycles = [1];
 923 }
 924 def: InstRW<[HWWriteResGroup9], (instregex "VPBLENDD(Y?)rri")>;
 925
 926 def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {
 927   let Latency = 1;
 928   let NumMicroOps = 1;
 929   let ResourceCycles = [1];
 930 }
 931 def: InstRW<[HWWriteResGroup10], (instrs CBW, CWDE, CDQE,
 932                                          CMC, STC,
 933                                          SGDT64m,
 934                                          SIDT64m,
 935                                          SMSW16m,
 936                                          STRm,
 937                                          SYSCALL)>;
 938
 939 def HWWriteResGroup11 : SchedWriteRes<[HWPort0,HWPort23]> {
 940   let Latency = 6;
 941   let NumMicroOps = 2;
 942   let ResourceCycles = [1,1];
 943 }
 944 def: InstRW<[HWWriteResGroup11], (instregex "(V?)CVTPS2PDrm")>;
 945
 946 def HWWriteResGroup11_1 : SchedWriteRes<[HWPort0,HWPort23]> {
 947   let Latency = 7;
 948   let NumMicroOps = 2;
 949   let ResourceCycles = [1,1];
 950 }
 951 def: InstRW<[HWWriteResGroup11_1], (instrs VPSLLVQrm, VPSRLVQrm)>;
 952 def: InstRW<[HWWriteResGroup11_1], (instregex "(V?)CVTSS2SDrm")>;
 953
 954 def HWWriteResGroup11_2 : SchedWriteRes<[HWPort0,HWPort23]> {
 955   let Latency = 8;
 956   let NumMicroOps = 2;
 957   let ResourceCycles = [1,1];
 958 }
 959 def: InstRW<[HWWriteResGroup11_2], (instrs VPSLLVQYrm, VPSRLVQYrm)>;
 960
 961 def HWWriteResGroup12 : SchedWriteRes<[HWPort1,HWPort23]> {
 962   let Latency = 8;
 963   let NumMicroOps = 2;
 964   let ResourceCycles = [1,1];
 965 }
 966 def: InstRW<[HWWriteResGroup12], (instrs MMX_CVTPI2PSirm)>;
 967 def: InstRW<[HWWriteResGroup12], (instregex "P(DEP|EXT)(32|64)rm")>;
 968
 969 def HWWriteResGroup13 : SchedWriteRes<[HWPort5,HWPort23]> {
 970   let Latency = 6;
 971   let NumMicroOps = 2;
 972   let ResourceCycles = [1,1];
 973 }
 974 def: InstRW<[HWWriteResGroup13], (instregex "(V?)PMOV(SX|ZX)BDrm",
 975                                             "(V?)PMOV(SX|ZX)BQrm",
 976                                             "(V?)PMOV(SX|ZX)BWrm",
 977                                             "(V?)PMOV(SX|ZX)DQrm",
 978                                             "(V?)PMOV(SX|ZX)WDrm",
 979                                             "(V?)PMOV(SX|ZX)WQrm")>;
 980
 981 def HWWriteResGroup13_1 : SchedWriteRes<[HWPort5,HWPort23]> {
 982   let Latency = 8;
 983   let NumMicroOps = 2;
 984   let ResourceCycles = [1,1];
 985 }
 986 def: InstRW<[HWWriteResGroup13_1], (instrs VPMOVSXBDYrm,
 987                                            VPMOVSXBQYrm,
 988                                            VPMOVSXWQYrm)>;
 989
 990 def HWWriteResGroup14 : SchedWriteRes<[HWPort6,HWPort23]> {
 991   let Latency = 6;
 992   let NumMicroOps = 2;
 993   let ResourceCycles = [1,1];
 994 }
 995 def: InstRW<[HWWriteResGroup14], (instrs FARJMP64)>;
 996 def: InstRW<[HWWriteResGroup14], (instregex "JMP(16|32|64)m")>;
 997
 998 def HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort15]> {
 999   let Latency = 6;
1000   let NumMicroOps = 2;
1001   let ResourceCycles = [1,1];
1002 }
1003 def: InstRW<[HWWriteResGroup16], (instregex "ANDN(32|64)rm",
1004                                             "MOVBE(16|32|64)rm")>;
1005
1006 def HWWriteResGroup17 : SchedWriteRes<[HWPort23,HWPort015]> {
1007   let Latency = 7;
1008   let NumMicroOps = 2;
1009   let ResourceCycles = [1,1];
1010 }
1011 def: InstRW<[HWWriteResGroup17], (instrs VINSERTF128rm,
1012                                          VINSERTI128rm,
1013                                          VPBLENDDrmi)>;
1014
1015 def HWWriteResGroup17_2 : SchedWriteRes<[HWPort23,HWPort015]> {
1016   let Latency = 8;
1017   let NumMicroOps = 2;
1018   let ResourceCycles = [1,1];
1019 }
1020 def: InstRW<[HWWriteResGroup17_2], (instrs VPBLENDDYrmi)>;
1021
1022 def HWWriteResGroup18 : SchedWriteRes<[HWPort23,HWPort0156]> {
1023   let Latency = 6;
1024   let NumMicroOps = 2;
1025   let ResourceCycles = [1,1];
1026 }
1027 def: InstRW<[HWWriteResGroup18], (instrs POP16r, POP32r, POP64r)>;
1028 def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)rmr")>;
1029
1030 def HWWriteResGroup19 : SchedWriteRes<[HWPort237,HWPort0156]> {
1031   let Latency = 2;
1032   let NumMicroOps = 2;
1033   let ResourceCycles = [1,1];
1034 }
1035 def: InstRW<[HWWriteResGroup19], (instrs SFENCE)>;
1036
1037 def HWWriteResGroup21 : SchedWriteRes<[HWPort4,HWPort6,HWPort237]> {
1038   let Latency = 2;
1039   let NumMicroOps = 3;
1040   let ResourceCycles = [1,1,1];
1041 }
1042 def: InstRW<[HWWriteResGroup21], (instrs FNSTCW16m)>;
1043
1044 def HWWriteResGroup23 : SchedWriteRes<[HWPort4,HWPort237,HWPort15]> {
1045   let Latency = 2;
1046   let NumMicroOps = 3;
1047   let ResourceCycles = [1,1,1];
1048 }
1049 def: InstRW<[HWWriteResGroup23], (instregex "MOVBE(32|64)mr")>;
1050
1051 def HWWriteResGroup23_16 : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
1052   let Latency = 2;
1053   let NumMicroOps = 3;
1054   let ResourceCycles = [1,1,1];
1055 }
1056 def: InstRW<[HWWriteResGroup23_16], (instrs MOVBE16mr)>;
1057
1058 def HWWriteResGroup24 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> {
1059   let Latency = 2;
1060   let NumMicroOps = 3;
1061   let ResourceCycles = [1,1,1];
1062 }
1063 def: InstRW<[HWWriteResGroup24], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
1064                                          STOSB, STOSL, STOSQ, STOSW)>;
1065 def: InstRW<[HWWriteResGroup24], (instregex "PUSH(16|32|64)rmr")>;
1066
1067 def HWWriteResGroup25 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> {
1068   let Latency = 7;
1069   let NumMicroOps = 4;
1070   let ResourceCycles = [1,1,1,1];
1071 }
1072 def: InstRW<[HWWriteResGroup25], (instregex "SAR(8|16|32|64)m(1|i)",
1073                                             "SHL(8|16|32|64)m(1|i)",
1074                                             "SHR(8|16|32|64)m(1|i)")>;
1075
1076 def HWWriteResGroup26 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
1077   let Latency = 7;
1078   let NumMicroOps = 4;
1079   let ResourceCycles = [1,1,1,1];
1080 }
1081 def: InstRW<[HWWriteResGroup26], (instregex "POP(16|32|64)rmm",
1082                                             "PUSH(16|32|64)rmm")>;
1083
1084 def HWWriteResGroup28 : SchedWriteRes<[HWPort01]> {
1085   let Latency = 2;
1086   let NumMicroOps = 2;
1087   let ResourceCycles = [2];
1088 }
1089 def: InstRW<[HWWriteResGroup28], (instrs FDECSTP)>;
1090
1091 def HWWriteResGroup30 : SchedWriteRes<[HWPort0156]> {
1092   let Latency = 2;
1093   let NumMicroOps = 2;
1094   let ResourceCycles = [2];
1095 }
1096 def: InstRW<[HWWriteResGroup30], (instrs LFENCE,
1097                                          MFENCE,
1098                                          WAIT,
1099                                          XGETBV)>;
1100
1101 def HWWriteResGroup31 : SchedWriteRes<[HWPort0,HWPort5]> {
1102   let Latency = 2;
1103   let NumMicroOps = 2;
1104   let ResourceCycles = [1,1];
1105 }
1106 def: InstRW<[HWWriteResGroup31], (instregex "(V?)CVTPS2PDrr",
1107                                             "(V?)CVTSS2SDrr")>;
1108
1109 def HWWriteResGroup32 : SchedWriteRes<[HWPort6,HWPort0156]> {
1110   let Latency = 2;
1111   let NumMicroOps = 2;
1112   let ResourceCycles = [1,1];
1113 }
1114 def: InstRW<[HWWriteResGroup32], (instregex "CLFLUSH")>;
1115
1116 def HWWriteResGroup33 : SchedWriteRes<[HWPort01,HWPort015]> {
1117   let Latency = 2;
1118   let NumMicroOps = 2;
1119   let ResourceCycles = [1,1];
1120 }
1121 def: InstRW<[HWWriteResGroup33], (instrs MMX_MOVDQ2Qrr)>;
1122
1123 def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> {
1124   let Latency = 2;
1125   let NumMicroOps = 2;
1126   let ResourceCycles = [1,1];
1127 }
1128 def: InstRW<[HWWriteResGroup35], (instrs CWD, JCXZ, JECXZ, JRCXZ)>;
1129
1130 def HWWriteResGroup36_2 : SchedWriteRes<[HWPort5,HWPort23]> {
1131   let Latency = 7;
1132   let NumMicroOps = 3;
1133   let ResourceCycles = [2,1];
1134 }
1135 def: InstRW<[HWWriteResGroup36_2], (instrs MMX_PACKSSDWirm,
1136                                            MMX_PACKSSWBirm,
1137                                            MMX_PACKUSWBirm)>;
1138
1139 def HWWriteResGroup37 : SchedWriteRes<[HWPort23,HWPort0156]> {
1140   let Latency = 7;
1141   let NumMicroOps = 3;
1142   let ResourceCycles = [1,2];
1143 }
1144 def: InstRW<[HWWriteResGroup37], (instrs LEAVE, LEAVE64,
1145                                          SCASB, SCASL, SCASQ, SCASW)>;
1146
1147 def HWWriteResGroup39 : SchedWriteRes<[HWPort0,HWPort01,HWPort23]> {
1148   let Latency = 7;
1149   let NumMicroOps = 3;
1150   let ResourceCycles = [1,1,1];
1151 }
1152 def: InstRW<[HWWriteResGroup39], (instrs FLDCW16m)>;
1153
1154 def HWWriteResGroup41 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> {
1155   let Latency = 7;
1156   let NumMicroOps = 3;
1157   let ResourceCycles = [1,1,1];
1158 }
1159 def: InstRW<[HWWriteResGroup41], (instrs LRETQ, RETL, RETQ)>;
1160
1161 def HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> {
1162   let Latency = 3;
1163   let NumMicroOps = 4;
1164   let ResourceCycles = [1,1,1,1];
1165 }
1166 def: InstRW<[HWWriteResGroup44], (instregex "CALL(16|32|64)r")>;
1167
1168 def HWWriteResGroup45 : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> {
1169   let Latency = 3;
1170   let NumMicroOps = 4;
1171   let ResourceCycles = [1,1,1,1];
1172 }
1173 def: InstRW<[HWWriteResGroup45], (instrs CALL64pcrel32)>;
1174
1175 def HWWriteResGroup46 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> {
1176   let Latency = 8;
1177   let NumMicroOps = 5;
1178   let ResourceCycles = [1,1,1,2];
1179 }
1180 def: InstRW<[HWWriteResGroup46], (instregex "ROL(8|16|32|64)m(1|i)",
1181                                             "ROR(8|16|32|64)m(1|i)")>;
1182
1183 def HWWriteResGroup46_1 : SchedWriteRes<[HWPort06]> {
1184   let Latency = 2;
1185   let NumMicroOps = 2;
1186   let ResourceCycles = [2];
1187 }
1188 def: InstRW<[HWWriteResGroup46_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
1189                                            ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
1190
1191 def HWWriteResGroup47 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
1192   let Latency = 8;
1193   let NumMicroOps = 5;
1194   let ResourceCycles = [1,1,1,2];
1195 }
1196 def: InstRW<[HWWriteResGroup47], (instregex "XADD(8|16|32|64)rm")>;
1197
1198 def HWWriteResGroup48 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
1199   let Latency = 8;
1200   let NumMicroOps = 5;
1201   let ResourceCycles = [1,1,1,1,1];
1202 }
1203 def: InstRW<[HWWriteResGroup48], (instregex "CALL(16|32|64)m")>;
1204 def: InstRW<[HWWriteResGroup48], (instrs FARCALL64)>;
1205
1206 def HWWriteResGroup50 : SchedWriteRes<[HWPort1]> {
1207   let Latency = 3;
1208   let NumMicroOps = 1;
1209   let ResourceCycles = [1];
1210 }
1211 def: InstRW<[HWWriteResGroup50], (instrs MMX_CVTPI2PSirr)>;
1212 def: InstRW<[HWWriteResGroup50], (instregex "P(DEP|EXT)(32|64)rr",
1213                                             "(V?)CVTDQ2PS(Y?)rr")>;
1214
1215 def HWWriteResGroup51 : SchedWriteRes<[HWPort5]> {
1216   let Latency = 3;
1217   let NumMicroOps = 1;
1218   let ResourceCycles = [1];
1219 }
1220 def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCAST(B|W)rr")>;
1221
1222 def HWWriteResGroup52 : SchedWriteRes<[HWPort1,HWPort23]> {
1223   let Latency = 9;
1224   let NumMicroOps = 2;
1225   let ResourceCycles = [1,1];
1226 }
1227 def: InstRW<[HWWriteResGroup52], (instregex "(V?)CVTPS2DQrm",
1228                                             "(V?)CVTTPS2DQrm")>;
1229
1230 def HWWriteResGroup52_1 : SchedWriteRes<[HWPort1,HWPort23]> {
1231   let Latency = 10;
1232   let NumMicroOps = 2;
1233   let ResourceCycles = [1,1];
1234 }
1235 def: InstRW<[HWWriteResGroup52_1], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1236                                               "ILD_F(16|32|64)m")>;
1237 def: InstRW<[HWWriteResGroup52_1], (instrs VCVTDQ2PSYrm,
1238                                            VCVTPS2DQYrm,
1239                                            VCVTTPS2DQYrm)>;
1240
1241 def HWWriteResGroup53_1 : SchedWriteRes<[HWPort5,HWPort23]> {
1242   let Latency = 9;
1243   let NumMicroOps = 2;
1244   let ResourceCycles = [1,1];
1245 }
1246 def: InstRW<[HWWriteResGroup53_1], (instrs VPMOVSXBWYrm,
1247                                            VPMOVSXDQYrm,
1248                                            VPMOVSXWDYrm,
1249                                            VPMOVZXWDYrm)>;
1250
1251 def HWWriteResGroup57 : SchedWriteRes<[HWPort5,HWPort0156]> {
1252   let Latency = 3;
1253   let NumMicroOps = 3;
1254   let ResourceCycles = [2,1];
1255 }
1256 def: InstRW<[HWWriteResGroup57], (instrs MMX_PACKSSDWirr,
1257                                          MMX_PACKSSWBirr,
1258                                          MMX_PACKUSWBirr)>;
1259
1260 def HWWriteResGroup58 : SchedWriteRes<[HWPort6,HWPort0156]> {
1261   let Latency = 3;
1262   let NumMicroOps = 3;
1263   let ResourceCycles = [1,2];
1264 }
1265 def: InstRW<[HWWriteResGroup58], (instregex "CLD")>;
1266
1267 def HWWriteResGroup59 : SchedWriteRes<[HWPort06,HWPort0156]> {
1268   let Latency = 3;
1269   let NumMicroOps = 3;
1270   let ResourceCycles = [1,2];
1271 }
1272 def: InstRW<[HWWriteResGroup59], (instregex "RCL(8|16|32|64)r(1|i)",
1273                                             "RCR(8|16|32|64)r(1|i)")>;
1274
1275 def HWWriteResGroup61 : SchedWriteRes<[HWPort0,HWPort4,HWPort237]> {
1276   let Latency = 4;
1277   let NumMicroOps = 3;
1278   let ResourceCycles = [1,1,1];
1279 }
1280 def: InstRW<[HWWriteResGroup61], (instrs FNSTSWm)>;
1281
1282 def HWWriteResGroup62 : SchedWriteRes<[HWPort1,HWPort4,HWPort237]> {
1283   let Latency = 4;
1284   let NumMicroOps = 3;
1285   let ResourceCycles = [1,1,1];
1286 }
1287 def: InstRW<[HWWriteResGroup62], (instregex "IST(T?)_FP(16|32|64)m",
1288                                             "IST_F(16|32)m")>;
1289
1290 def HWWriteResGroup66 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> {
1291   let Latency = 9;
1292   let NumMicroOps = 5;
1293   let ResourceCycles = [1,1,1,2];
1294 }
1295 def: InstRW<[HWWriteResGroup66], (instregex "RCL(8|16|32|64)m(1|i)",
1296                                             "RCR(8|16|32|64)m(1|i)")>;
1297
1298 def HWWriteResGroup68 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
1299   let Latency = 9;
1300   let NumMicroOps = 6;
1301   let ResourceCycles = [1,1,1,3];
1302 }
1303 def: InstRW<[HWWriteResGroup68], (instregex "XCHG(8|16|32|64)rm")>;
1304
1305 def HWWriteResGroup69 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort0156]> {
1306   let Latency = 9;
1307   let NumMicroOps = 6;
1308   let ResourceCycles = [1,1,1,2,1];
1309 }
1310 def: InstRW<[HWWriteResGroup69], (instregex "ROL(8|16|32|64)mCL",
1311                                             "ROR(8|16|32|64)mCL",
1312                                             "SAR(8|16|32|64)mCL",
1313                                             "SHL(8|16|32|64)mCL",
1314                                             "SHR(8|16|32|64)mCL")>;
1315 def: SchedAlias<WriteADCRMW, HWWriteResGroup69>;
1316
1317 def HWWriteResGroup70 : SchedWriteRes<[HWPort0,HWPort1]> {
1318   let Latency = 4;
1319   let NumMicroOps = 2;
1320   let ResourceCycles = [1,1];
1321 }
1322 def: InstRW<[HWWriteResGroup70], (instregex "(V?)CVT(T?)SD2SI(64)?rr",
1323                                             "(V?)CVT(T?)SS2SI(64)?rr")>;
1324
1325 def HWWriteResGroup71 : SchedWriteRes<[HWPort0,HWPort5]> {
1326   let Latency = 4;
1327   let NumMicroOps = 2;
1328   let ResourceCycles = [1,1];
1329 }
1330 def: InstRW<[HWWriteResGroup71], (instrs VCVTPS2PDYrr)>;
1331
1332 def HWWriteResGroup72 : SchedWriteRes<[HWPort0,HWPort0156]> {
1333   let Latency = 4;
1334   let NumMicroOps = 2;
1335   let ResourceCycles = [1,1];
1336 }
1337 def: InstRW<[HWWriteResGroup72], (instrs FNSTSW16r)>;
1338
1339 def HWWriteResGroup73 : SchedWriteRes<[HWPort1,HWPort5]> {
1340   let Latency = 4;
1341   let NumMicroOps = 2;
1342   let ResourceCycles = [1,1];
1343 }
1344 def: InstRW<[HWWriteResGroup73], (instrs MMX_CVTPI2PDirr,
1345                                          MMX_CVTPD2PIirr,
1346                                          MMX_CVTPS2PIirr,
1347                                          MMX_CVTTPD2PIirr,
1348                                          MMX_CVTTPS2PIirr)>;
1349 def: InstRW<[HWWriteResGroup73], (instregex "(V?)CVTDQ2PDrr",
1350                                             "(V?)CVTPD2PSrr",
1351                                             "(V?)CVTSD2SSrr",
1352                                             "(V?)CVTSI(64)?2SDrr",
1353                                             "(V?)CVTSI2SSrr",
1354                                             "(V?)CVT(T?)PD2DQrr")>;
1355
1356 def HWWriteResGroup75 : SchedWriteRes<[HWPort1,HWPort23]> {
1357   let Latency = 11;
1358   let NumMicroOps = 3;
1359   let ResourceCycles = [2,1];
1360 }
1361 def: InstRW<[HWWriteResGroup75], (instregex "FICOM(P?)(16|32)m")>;
1362
1363 def HWWriteResGroup76 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
1364   let Latency = 9;
1365   let NumMicroOps = 3;
1366   let ResourceCycles = [1,1,1];
1367 }
1368 def: InstRW<[HWWriteResGroup76], (instregex "(V?)CVTSD2SI(64)?rm",
1369                                             "(V?)CVTSS2SI(64)?rm",
1370                                             "(V?)CVTTSD2SI(64)?rm",
1371                                             "VCVTTSS2SI64rm",
1372                                             "(V?)CVTTSS2SIrm")>;
1373
1374 def HWWriteResGroup77 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> {
1375   let Latency = 10;
1376   let NumMicroOps = 3;
1377   let ResourceCycles = [1,1,1];
1378 }
1379 def: InstRW<[HWWriteResGroup77], (instrs VCVTPS2PDYrm)>;
1380
1381 def HWWriteResGroup78 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
1382   let Latency = 10;
1383   let NumMicroOps = 3;
1384   let ResourceCycles = [1,1,1];
1385 }
1386 def: InstRW<[HWWriteResGroup78], (instrs CVTPD2PSrm,
1387                                          CVTPD2DQrm,
1388                                          CVTTPD2DQrm,
1389                                          MMX_CVTPD2PIirm,
1390                                          MMX_CVTTPD2PIirm,
1391                                          CVTDQ2PDrm,
1392                                          VCVTDQ2PDrm)>;
1393
1394 def HWWriteResGroup78_1 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
1395   let Latency = 9;
1396   let NumMicroOps = 3;
1397   let ResourceCycles = [1,1,1];
1398 }
1399 def: InstRW<[HWWriteResGroup78_1], (instrs MMX_CVTPI2PDirm,
1400                                            CVTSD2SSrm, CVTSD2SSrm_Int,
1401                                            VCVTSD2SSrm, VCVTSD2SSrm_Int)>;
1402
1403 def HWWriteResGroup80 : SchedWriteRes<[HWPort5,HWPort23,HWPort015]> {
1404   let Latency = 9;
1405   let NumMicroOps = 3;
1406   let ResourceCycles = [1,1,1];
1407 }
1408 def: InstRW<[HWWriteResGroup80], (instregex "VPBROADCAST(B|W)(Y?)rm")>;
1409
1410 def HWWriteResGroup81 : SchedWriteRes<[HWPort0156]> {
1411   let Latency = 4;
1412   let NumMicroOps = 4;
1413   let ResourceCycles = [4];
1414 }
1415 def: InstRW<[HWWriteResGroup81], (instrs FNCLEX)>;
1416
1417 def HWWriteResGroup82 : SchedWriteRes<[]> {
1418   let Latency = 0;
1419   let NumMicroOps = 4;
1420   let ResourceCycles = [];
1421 }
1422 def: InstRW<[HWWriteResGroup82], (instrs VZEROUPPER)>;
1423
1424 def HWWriteResGroup83 : SchedWriteRes<[HWPort1,HWPort6,HWPort0156]> {
1425   let Latency = 4;
1426   let NumMicroOps = 4;
1427   let ResourceCycles = [1,1,2];
1428 }
1429 def: InstRW<[HWWriteResGroup83], (instregex "LAR(16|32|64)rr")>;
1430
1431 def HWWriteResGroup87 : SchedWriteRes<[HWPort1,HWPort6,HWPort23,HWPort0156]> {
1432   let Latency = 9;
1433   let NumMicroOps = 5;
1434   let ResourceCycles = [1,2,1,1];
1435 }
1436 def: InstRW<[HWWriteResGroup87], (instregex "LAR(16|32|64)rm",
1437                                             "LSL(16|32|64)rm")>;
1438
1439 def HWWriteResGroup88 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> {
1440   let Latency = 5;
1441   let NumMicroOps = 6;
1442   let ResourceCycles = [1,1,4];
1443 }
1444 def: InstRW<[HWWriteResGroup88], (instregex "PUSHF(16|64)")>;
1445
1446 def HWWriteResGroup89 : SchedWriteRes<[HWPort0]> {
1447   let Latency = 5;
1448   let NumMicroOps = 1;
1449   let ResourceCycles = [1];
1450 }
1451 def: InstRW<[HWWriteResGroup89], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
1452
1453 def HWWriteResGroup91_2 : SchedWriteRes<[HWPort0,HWPort23]> {
1454   let Latency = 11;
1455   let NumMicroOps = 2;
1456   let ResourceCycles = [1,1];
1457 }
1458 def: InstRW<[HWWriteResGroup91_2], (instregex "(V?)PCMPGTQrm")>;
1459
1460 def HWWriteResGroup91_3 : SchedWriteRes<[HWPort0,HWPort23]> {
1461   let Latency = 12;
1462   let NumMicroOps = 2;
1463   let ResourceCycles = [1,1];
1464 }
1465 def: InstRW<[HWWriteResGroup91_3], (instregex "MUL_F(32|64)m")>;
1466 def: InstRW<[HWWriteResGroup91_3], (instrs VPCMPGTQYrm)>;
1467
1468 def HWWriteResGroup93 : SchedWriteRes<[HWPort1,HWPort5]> {
1469   let Latency = 5;
1470   let NumMicroOps = 3;
1471   let ResourceCycles = [1,2];
1472 }
1473 def: InstRW<[HWWriteResGroup93], (instregex "(V?)CVTSI642SSrr")>;
1474
1475 def HWWriteResGroup94 : SchedWriteRes<[HWPort1,HWPort6,HWPort06]> {
1476   let Latency = 5;
1477   let NumMicroOps = 3;
1478   let ResourceCycles = [1,1,1];
1479 }
1480 def: InstRW<[HWWriteResGroup94], (instregex "STR(16|32|64)r")>;
1481
1482 def HWWriteResGroup97 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort23]> {
1483   let Latency = 10;
1484   let NumMicroOps = 4;
1485   let ResourceCycles = [1,1,1,1];
1486 }
1487 def: InstRW<[HWWriteResGroup97], (instregex "CVTTSS2SI64rm")>;
1488
1489 def HWWriteResGroup99 : SchedWriteRes<[HWPort6,HWPort0156]> {
1490   let Latency = 5;
1491   let NumMicroOps = 5;
1492   let ResourceCycles = [1,4];
1493 }
1494 def: InstRW<[HWWriteResGroup99], (instrs PAUSE)>;
1495
1496 def HWWriteResGroup100 : SchedWriteRes<[HWPort06,HWPort0156]> {
1497   let Latency = 5;
1498   let NumMicroOps = 5;
1499   let ResourceCycles = [1,4];
1500 }
1501 def: InstRW<[HWWriteResGroup100], (instrs XSETBV)>;
1502
1503 def HWWriteResGroup102 : SchedWriteRes<[HWPort1,HWPort5]> {
1504   let Latency = 6;
1505   let NumMicroOps = 2;
1506   let ResourceCycles = [1,1];
1507 }
1508 def: InstRW<[HWWriteResGroup102], (instrs VCVTDQ2PDYrr,
1509                                           VCVTPD2PSYrr,
1510                                           VCVTPD2DQYrr,
1511                                           VCVTTPD2DQYrr)>;
1512
1513 def HWWriteResGroup103 : SchedWriteRes<[HWPort1,HWPort23]> {
1514   let Latency = 13;
1515   let NumMicroOps = 3;
1516   let ResourceCycles = [2,1];
1517 }
1518 def: InstRW<[HWWriteResGroup103], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
1519
1520 def HWWriteResGroup104 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
1521   let Latency = 12;
1522   let NumMicroOps = 3;
1523   let ResourceCycles = [1,1,1];
1524 }
1525 def: InstRW<[HWWriteResGroup104], (instrs VCVTDQ2PDYrm)>;
1526
1527 def HWWriteResGroup107 : SchedWriteRes<[HWPort1,HWPort6,HWPort06,HWPort0156]> {
1528   let Latency = 6;
1529   let NumMicroOps = 4;
1530   let ResourceCycles = [1,1,1,1];
1531 }
1532 def: InstRW<[HWWriteResGroup107], (instregex "SLDT(16|32|64)r")>;
1533
1534 def HWWriteResGroup108 : SchedWriteRes<[HWPort6,HWPort0156]> {
1535   let Latency = 6;
1536   let NumMicroOps = 6;
1537   let ResourceCycles = [1,5];
1538 }
1539 def: InstRW<[HWWriteResGroup108], (instrs STD)>;
1540
1541 def HWWriteResGroup114 : SchedWriteRes<[HWPort6,HWPort06,HWPort15,HWPort0156]> {
1542   let Latency = 7;
1543   let NumMicroOps = 7;
1544   let ResourceCycles = [2,2,1,2];
1545 }
1546 def: InstRW<[HWWriteResGroup114], (instrs LOOP)>;
1547
1548 def HWWriteResGroup115 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
1549   let Latency = 15;
1550   let NumMicroOps = 3;
1551   let ResourceCycles = [1,1,1];
1552 }
1553 def: InstRW<[HWWriteResGroup115], (instregex "MUL_FI(16|32)m")>;
1554
1555 def HWWriteResGroup120 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {
1556   let Latency = 16;
1557   let NumMicroOps = 10;
1558   let ResourceCycles = [1,1,1,4,1,2];
1559 }
1560 def: InstRW<[HWWriteResGroup120], (instregex "RCL(8|16|32|64)mCL")>;
1561
1562 def HWWriteResGroup129 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> {
1563   let Latency = 11;
1564   let NumMicroOps = 7;
1565   let ResourceCycles = [2,2,3];
1566 }
1567 def: InstRW<[HWWriteResGroup129], (instregex "RCL(16|32|64)rCL",
1568                                              "RCR(16|32|64)rCL")>;
1569
1570 def HWWriteResGroup130 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> {
1571   let Latency = 11;
1572   let NumMicroOps = 9;
1573   let ResourceCycles = [1,4,1,3];
1574 }
1575 def: InstRW<[HWWriteResGroup130], (instrs RCL8rCL)>;
1576
1577 def HWWriteResGroup131 : SchedWriteRes<[HWPort06,HWPort0156]> {
1578   let Latency = 11;
1579   let NumMicroOps = 11;
1580   let ResourceCycles = [2,9];
1581 }
1582 def: InstRW<[HWWriteResGroup131], (instrs LOOPE, LOOPNE)>;
1583
1584 def HWWriteResGroup132 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {
1585   let Latency = 17;
1586   let NumMicroOps = 14;
1587   let ResourceCycles = [1,1,1,4,2,5];
1588 }
1589 def: InstRW<[HWWriteResGroup132], (instrs CMPXCHG8B)>;
1590
1591 def HWWriteResGroup135 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> {
1592   let Latency = 19;
1593   let NumMicroOps = 11;
1594   let ResourceCycles = [2,1,1,3,1,3];
1595 }
1596 def: InstRW<[HWWriteResGroup135], (instregex "RCR(8|16|32|64)mCL")>;
1597
1598 def HWWriteResGroup142 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> {
1599   let Latency = 14;
1600   let NumMicroOps = 10;
1601   let ResourceCycles = [2,3,1,4];
1602 }
1603 def: InstRW<[HWWriteResGroup142], (instrs RCR8rCL)>;
1604
1605 def HWWriteResGroup143 : SchedWriteRes<[HWPort23,HWPort0156]> {
1606   let Latency = 19;
1607   let NumMicroOps = 15;
1608   let ResourceCycles = [1,14];
1609 }
1610 def: InstRW<[HWWriteResGroup143], (instrs POPF16)>;
1611
1612 def HWWriteResGroup144 : SchedWriteRes<[HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> {
1613   let Latency = 21;
1614   let NumMicroOps = 8;
1615   let ResourceCycles = [1,1,1,1,1,1,2];
1616 }
1617 def: InstRW<[HWWriteResGroup144], (instrs INSB, INSL, INSW)>;
1618
1619 def HWWriteResGroup145 : SchedWriteRes<[HWPort5, HWPort6]> {
1620   let Latency = 8;
1621   let NumMicroOps = 20;
1622   let ResourceCycles = [1,1];
1623 }
1624 def: InstRW<[HWWriteResGroup145], (instrs VZEROALL)>;
1625
1626 def HWWriteResGroup146 : SchedWriteRes<[HWPort0,HWPort4,HWPort5,HWPort23,HWPort237,HWPort06,HWPort0156]> {
1627   let Latency = 22;
1628   let NumMicroOps = 19;
1629   let ResourceCycles = [2,1,4,1,1,4,6];
1630 }
1631 def: InstRW<[HWWriteResGroup146], (instrs CMPXCHG16B)>;
1632
1633 def HWWriteResGroup147 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156]> {
1634   let Latency = 17;
1635   let NumMicroOps = 15;
1636   let ResourceCycles = [2,1,2,4,2,4];
1637 }
1638 def: InstRW<[HWWriteResGroup147], (instrs XCH_F)>;
1639
1640 def HWWriteResGroup149 : SchedWriteRes<[HWPort5,HWPort6,HWPort06,HWPort0156]> {
1641   let Latency = 18;
1642   let NumMicroOps = 8;
1643   let ResourceCycles = [1,1,1,5];
1644 }
1645 def: InstRW<[HWWriteResGroup149], (instrs CPUID, RDTSC)>;
1646
1647 def HWWriteResGroup151 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> {
1648   let Latency = 23;
1649   let NumMicroOps = 19;
1650   let ResourceCycles = [3,1,15];
1651 }
1652 def: InstRW<[HWWriteResGroup151], (instregex "XRSTOR(64)?")>;
1653
1654 def HWWriteResGroup154 : SchedWriteRes<[HWPort0]> {
1655   let Latency = 20;
1656   let NumMicroOps = 1;
1657   let ResourceCycles = [1];
1658 }
1659 def: InstRW<[HWWriteResGroup154], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
1660
1661 def HWWriteResGroup155 : SchedWriteRes<[HWPort0,HWPort23]> {
1662   let Latency = 27;
1663   let NumMicroOps = 2;
1664   let ResourceCycles = [1,1];
1665 }
1666 def: InstRW<[HWWriteResGroup155], (instregex "DIVR_F(32|64)m")>;
1667
1668 def HWWriteResGroup156 : SchedWriteRes<[HWPort5,HWPort6,HWPort0156]> {
1669   let Latency = 20;
1670   let NumMicroOps = 10;
1671   let ResourceCycles = [1,2,7];
1672 }
1673 def: InstRW<[HWWriteResGroup156], (instrs MWAITrr)>;
1674
1675 def HWWriteResGroup161 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
1676   let Latency = 30;
1677   let NumMicroOps = 3;
1678   let ResourceCycles = [1,1,1];
1679 }
1680 def: InstRW<[HWWriteResGroup161], (instregex "DIVR_FI(16|32)m")>;
1681
1682 def HWWriteResGroup162 : SchedWriteRes<[HWPort0]> {
1683   let Latency = 24;
1684   let NumMicroOps = 1;
1685   let ResourceCycles = [1];
1686 }
1687 def: InstRW<[HWWriteResGroup162], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
1688
1689 def HWWriteResGroup163 : SchedWriteRes<[HWPort0,HWPort23]> {
1690   let Latency = 31;
1691   let NumMicroOps = 2;
1692   let ResourceCycles = [1,1];
1693 }
1694 def: InstRW<[HWWriteResGroup163], (instregex "DIV_F(32|64)m")>;
1695
1696 def HWWriteResGroup164 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
1697   let Latency = 30;
1698   let NumMicroOps = 27;
1699   let ResourceCycles = [1,5,1,1,19];
1700 }
1701 def: InstRW<[HWWriteResGroup164], (instrs XSAVE64)>;
1702
1703 def HWWriteResGroup165 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
1704   let Latency = 31;
1705   let NumMicroOps = 28;
1706   let ResourceCycles = [1,6,1,1,19];
1707 }
1708 def: InstRW<[HWWriteResGroup165], (instrs XSAVE)>;
1709 def: InstRW<[HWWriteResGroup165], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
1710
1711 def HWWriteResGroup166 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> {
1712   let Latency = 34;
1713   let NumMicroOps = 3;
1714   let ResourceCycles = [1,1,1];
1715 }
1716 def: InstRW<[HWWriteResGroup166], (instregex "DIV_FI(16|32)m")>;
1717
1718 def HWWriteResGroup170 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort06,HWPort0156]> {
1719   let Latency = 35;
1720   let NumMicroOps = 23;
1721   let ResourceCycles = [1,5,3,4,10];
1722 }
1723 def: InstRW<[HWWriteResGroup170], (instregex "IN(8|16|32)ri",
1724                                              "IN(8|16|32)rr")>;
1725
1726 def HWWriteResGroup171 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> {
1727   let Latency = 36;
1728   let NumMicroOps = 23;
1729   let ResourceCycles = [1,5,2,1,4,10];
1730 }
1731 def: InstRW<[HWWriteResGroup171], (instregex "OUT(8|16|32)ir",
1732                                              "OUT(8|16|32)rr")>;
1733
1734 def HWWriteResGroup175 : SchedWriteRes<[HWPort1,HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort15,HWPort0156]> {
1735   let Latency = 41;
1736   let NumMicroOps = 18;
1737   let ResourceCycles = [1,1,2,3,1,1,1,8];
1738 }
1739 def: InstRW<[HWWriteResGroup175], (instrs VMCLEARm)>;
1740
1741 def HWWriteResGroup176 : SchedWriteRes<[HWPort5,HWPort0156]> {
1742   let Latency = 42;
1743   let NumMicroOps = 22;
1744   let ResourceCycles = [2,20];
1745 }
1746 def: InstRW<[HWWriteResGroup176], (instrs RDTSCP)>;
1747
1748 def HWWriteResGroup177 : SchedWriteRes<[HWPort0,HWPort01,HWPort23,HWPort05,HWPort06,HWPort015,HWPort0156]> {
1749   let Latency = 61;
1750   let NumMicroOps = 64;
1751   let ResourceCycles = [2,2,8,1,10,2,39];
1752 }
1753 def: InstRW<[HWWriteResGroup177], (instrs FLDENVm)>;
1754
1755 def HWWriteResGroup178 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> {
1756   let Latency = 64;
1757   let NumMicroOps = 88;
1758   let ResourceCycles = [4,4,31,1,2,1,45];
1759 }
1760 def: InstRW<[HWWriteResGroup178], (instrs FXRSTOR64)>;
1761
1762 def HWWriteResGroup179 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> {
1763   let Latency = 64;
1764   let NumMicroOps = 90;
1765   let ResourceCycles = [4,2,33,1,2,1,47];
1766 }
1767 def: InstRW<[HWWriteResGroup179], (instrs FXRSTOR)>;
1768
1769 def HWWriteResGroup180 : SchedWriteRes<[HWPort5,HWPort01,HWPort0156]> {
1770   let Latency = 75;
1771   let NumMicroOps = 15;
1772   let ResourceCycles = [6,3,6];
1773 }
1774 def: InstRW<[HWWriteResGroup180], (instrs FNINIT)>;
1775
1776 def HWWriteResGroup183 : SchedWriteRes<[HWPort0,HWPort1,HWPort4,HWPort5,HWPort6,HWPort237,HWPort06,HWPort0156]> {
1777   let Latency = 115;
1778   let NumMicroOps = 100;
1779   let ResourceCycles = [9,9,11,8,1,11,21,30];
1780 }
1781 def: InstRW<[HWWriteResGroup183], (instrs FSTENVm)>;
1782
1783 def HWWriteResGroup184 : SchedWriteRes<[HWPort0, HWPort5, HWPort15, HWPort015, HWPort06, HWPort23]> {
1784   let Latency = 26;
1785   let NumMicroOps = 12;
1786   let ResourceCycles = [2,2,1,3,2,2];
1787 }
1788 def: InstRW<[HWWriteResGroup184], (instrs VGATHERDPDrm,
1789                                           VPGATHERDQrm,
1790                                           VPGATHERDDrm)>;
1791
1792 def HWWriteResGroup185 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
1793   let Latency = 24;
1794   let NumMicroOps = 22;
1795   let ResourceCycles = [5,3,4,1,5,4];
1796 }
1797 def: InstRW<[HWWriteResGroup185], (instrs VGATHERQPDYrm,
1798                                           VPGATHERQQYrm)>;
1799
1800 def HWWriteResGroup186 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
1801   let Latency = 28;
1802   let NumMicroOps = 22;
1803   let ResourceCycles = [5,3,4,1,5,4];
1804 }
1805 def: InstRW<[HWWriteResGroup186], (instrs VPGATHERQDYrm)>;
1806
1807 def HWWriteResGroup187 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
1808   let Latency = 25;
1809   let NumMicroOps = 22;
1810   let ResourceCycles = [5,3,4,1,5,4];
1811 }
1812 def: InstRW<[HWWriteResGroup187], (instrs VPGATHERQDrm)>;
1813
1814 def HWWriteResGroup188 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
1815   let Latency = 27;
1816   let NumMicroOps = 20;
1817   let ResourceCycles = [3,3,4,1,5,4];
1818 }
1819 def: InstRW<[HWWriteResGroup188], (instrs VGATHERDPDYrm,
1820                                           VPGATHERDQYrm)>;
1821
1822 def HWWriteResGroup189 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
1823   let Latency = 27;
1824   let NumMicroOps = 34;
1825   let ResourceCycles = [5,3,8,1,9,8];
1826 }
1827 def: InstRW<[HWWriteResGroup189], (instrs VGATHERDPSYrm,
1828                                           VPGATHERDDYrm)>;
1829
1830 def HWWriteResGroup190 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
1831   let Latency = 23;
1832   let NumMicroOps = 14;
1833   let ResourceCycles = [3,3,2,1,3,2];
1834 }
1835 def: InstRW<[HWWriteResGroup190], (instrs VGATHERQPDrm,
1836                                           VPGATHERQQrm)>;
1837
1838 def HWWriteResGroup191 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
1839   let Latency = 28;
1840   let NumMicroOps = 15;
1841   let ResourceCycles = [3,3,2,1,4,2];
1842 }
1843 def: InstRW<[HWWriteResGroup191], (instrs VGATHERQPSYrm)>;
1844
1845 def HWWriteResGroup192 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
1846   let Latency = 25;
1847   let NumMicroOps = 15;
1848   let ResourceCycles = [3,3,2,1,4,2];
1849 }
1850 def: InstRW<[HWWriteResGroup192], (instrs VGATHERQPSrm,
1851                                           VGATHERDPSrm)>;
1852
1853 def: InstRW<[WriteZero], (instrs CLC)>;
1854
1855
1856 // Intruction variants handled by the renamer. These might not need execution
1857 // ports in certain conditions.
1858 // See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
1859 // section "Haswell and Broadwell Pipeline" > "Register allocation and
1860 // renaming".
1861 // These can be investigated with llvm-exegesis, e.g.
1862 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1863 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1864
1865 def HWWriteZeroLatency : SchedWriteRes<[]> {
1866   let Latency = 0;
1867 }
1868
1869 def HWWriteZeroIdiom : SchedWriteVariant<[
1870     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1871     SchedVar<NoSchedPred,                          [WriteALU]>
1872 ]>;
1873 def : InstRW<[HWWriteZeroIdiom], (instrs SUB32rr, SUB64rr,
1874                                          XOR32rr, XOR64rr)>;
1875
1876 def HWWriteFZeroIdiom : SchedWriteVariant<[
1877     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1878     SchedVar<NoSchedPred,                          [WriteFLogic]>
1879 ]>;
1880 def : InstRW<[HWWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr,
1881                                           VXORPDrr)>;
1882
1883 def HWWriteFZeroIdiomY : SchedWriteVariant<[
1884     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1885     SchedVar<NoSchedPred,                          [WriteFLogicY]>
1886 ]>;
1887 def : InstRW<[HWWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>;
1888
1889 def HWWriteVZeroIdiomLogicX : SchedWriteVariant<[
1890     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1891     SchedVar<NoSchedPred,                          [WriteVecLogicX]>
1892 ]>;
1893 def : InstRW<[HWWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>;
1894
1895 def HWWriteVZeroIdiomLogicY : SchedWriteVariant<[
1896     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1897     SchedVar<NoSchedPred,                          [WriteVecLogicY]>
1898 ]>;
1899 def : InstRW<[HWWriteVZeroIdiomLogicY], (instrs VPXORYrr)>;
1900
1901 def HWWriteVZeroIdiomALUX : SchedWriteVariant<[
1902     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1903     SchedVar<NoSchedPred,                          [WriteVecALUX]>
1904 ]>;
1905 def : InstRW<[HWWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr,
1906                                               PSUBDrr, VPSUBDrr,
1907                                               PSUBQrr, VPSUBQrr,
1908                                               PSUBWrr, VPSUBWrr,
1909                                               PCMPGTBrr, VPCMPGTBrr,
1910                                               PCMPGTDrr, VPCMPGTDrr,
1911                                               PCMPGTWrr, VPCMPGTWrr)>;
1912
1913 def HWWriteVZeroIdiomALUY : SchedWriteVariant<[
1914     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1915     SchedVar<NoSchedPred,                          [WriteVecALUY]>
1916 ]>;
1917 def : InstRW<[HWWriteVZeroIdiomALUY], (instrs VPSUBBYrr,
1918                                               VPSUBDYrr,
1919                                               VPSUBQYrr,
1920                                               VPSUBWYrr,
1921                                               VPCMPGTBYrr,
1922                                               VPCMPGTDYrr,
1923                                               VPCMPGTWYrr)>;
1924
1925 def HWWritePCMPGTQ : SchedWriteRes<[HWPort0]> {
1926   let Latency = 5;
1927   let NumMicroOps = 1;
1928   let ResourceCycles = [1];
1929 }
1930
1931 def HWWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
1932     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>,
1933     SchedVar<NoSchedPred,                          [HWWritePCMPGTQ]>
1934 ]>;
1935 def : InstRW<[HWWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
1936                                                  VPCMPGTQYrr)>;
1937
1938
1939 // The 0x83 ADC/SBB opcodes have special support for immediate 0 to only require
1940 // a single uop. It does not apply to the GR8 encoding. And only applies to the
1941 // 8-bit immediate since using larger immediate for 0 would be silly.
1942 // Unfortunately, this optimization does not apply to the AX/EAX/RAX short
1943 // encodings we convert to in MCInstLowering so we exclude AX/EAX/RAX here since
1944 // we schedule before that point.
1945 // TODO: Should we disable using the short encodings on these CPUs?
1946 def HWFastADC0 : MCSchedPredicate<
1947   CheckAll<[
1948     CheckImmOperand<2, 0>,              // Second MCOperand is Imm and has value 0.
1949     CheckNot<CheckRegOperand<1, AX>>,   // First MCOperand is not register AX
1950     CheckNot<CheckRegOperand<1, EAX>>,  // First MCOperand is not register EAX
1951     CheckNot<CheckRegOperand<1, RAX>>   // First MCOperand is not register RAX
1952   ]>
1953 >;
1954
1955 def HWWriteADC0 : SchedWriteRes<[HWPort06]> {
1956   let Latency = 1;
1957   let NumMicroOps = 1;
1958   let ResourceCycles = [1];
1959 }
1960
1961 def HWWriteADC : SchedWriteVariant<[
1962   SchedVar<HWFastADC0, [HWWriteADC0]>,
1963   SchedVar<NoSchedPred, [WriteADC]>
1964 ]>;
1965
1966 def : InstRW<[HWWriteADC], (instrs ADC16ri8, ADC32ri8, ADC64ri8,
1967                                       SBB16ri8, SBB32ri8, SBB64ri8)>;
1968
1969 // CMOVs that use both Z and C flag require an extra uop.
1970 def HWWriteCMOVA_CMOVBErr : SchedWriteRes<[HWPort06,HWPort0156]> {
1971   let Latency = 3;
1972   let ResourceCycles = [1,2];
1973   let NumMicroOps = 3;
1974 }
1975
1976 def HWWriteCMOVA_CMOVBErm : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> {
1977   let Latency = 8;
1978   let ResourceCycles = [1,1,2];
1979   let NumMicroOps = 4;
1980 }
1981
1982 def HWCMOVA_CMOVBErr :  SchedWriteVariant<[
1983   SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [HWWriteCMOVA_CMOVBErr]>,
1984   SchedVar<NoSchedPred,                             [WriteCMOV]>
1985 ]>;
1986
1987 def HWCMOVA_CMOVBErm :  SchedWriteVariant<[
1988   SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [HWWriteCMOVA_CMOVBErm]>,
1989   SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
1990 ]>;
1991
1992 def : InstRW<[HWCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
1993 def : InstRW<[HWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
1994
1995 // SETCCs that use both Z and C flag require an extra uop.
1996 def HWWriteSETA_SETBEr : SchedWriteRes<[HWPort06,HWPort0156]> {
1997   let Latency = 2;
1998   let ResourceCycles = [1,1];
1999   let NumMicroOps = 2;
2000 }
2001
2002 def HWWriteSETA_SETBEm : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> {
2003   let Latency = 3;
2004   let ResourceCycles = [1,1,1,1];
2005   let NumMicroOps = 4;
2006 }
2007
2008 def HWSETA_SETBErr :  SchedWriteVariant<[
2009   SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [HWWriteSETA_SETBEr]>,
2010   SchedVar<NoSchedPred,                         [WriteSETCC]>
2011 ]>;
2012
2013 def HWSETA_SETBErm :  SchedWriteVariant<[
2014   SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [HWWriteSETA_SETBEm]>,
2015   SchedVar<NoSchedPred,                         [WriteSETCCStore]>
2016 ]>;
2017
2018 def : InstRW<[HWSETA_SETBErr], (instrs SETCCr)>;
2019 def : InstRW<[HWSETA_SETBErm], (instrs SETCCm)>;
2020
2021 } // SchedModel