lib/Target/X86/X86Subtarget.cpp

   1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements the X86 specific subclass of TargetSubtargetInfo.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "X86.h"
  14
  15 #include "X86CallLowering.h"
  16 #include "X86LegalizerInfo.h"
  17 #include "X86MacroFusion.h"
  18 #include "X86RegisterBankInfo.h"
  19 #include "X86Subtarget.h"
  20 #include "MCTargetDesc/X86BaseInfo.h"
  21 #include "X86TargetMachine.h"
  22 #include "llvm/ADT/Triple.h"
  23 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
  24 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
  25 #include "llvm/IR/Attributes.h"
  26 #include "llvm/IR/ConstantRange.h"
  27 #include "llvm/IR/Function.h"
  28 #include "llvm/IR/GlobalValue.h"
  29 #include "llvm/Support/Casting.h"
  30 #include "llvm/Support/CodeGen.h"
  31 #include "llvm/Support/CommandLine.h"
  32 #include "llvm/Support/Debug.h"
  33 #include "llvm/Support/ErrorHandling.h"
  34 #include "llvm/Support/raw_ostream.h"
  35 #include "llvm/Target/TargetMachine.h"
  36
  37 #if defined(_MSC_VER)
  38 #include <intrin.h>
  39 #endif
  40
  41 using namespace llvm;
  42
  43 #define DEBUG_TYPE "subtarget"
  44
  45 #define GET_SUBTARGETINFO_TARGET_DESC
  46 #define GET_SUBTARGETINFO_CTOR
  47 #include "X86GenSubtargetInfo.inc"
  48
  49 // Temporary option to control early if-conversion for x86 while adding machine
  50 // models.
  51 static cl::opt<bool>
  52 X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
  53                cl::desc("Enable early if-conversion on X86"));
  54
  55
  56 /// Classify a blockaddress reference for the current subtarget according to how
  57 /// we should reference it in a non-pcrel context.
  58 unsigned char X86Subtarget::classifyBlockAddressReference() const {
  59   return classifyLocalReference(nullptr);
  60 }
  61
  62 /// Classify a global variable reference for the current subtarget according to
  63 /// how we should reference it in a non-pcrel context.
  64 unsigned char
  65 X86Subtarget::classifyGlobalReference(const GlobalValue *GV) const {
  66   return classifyGlobalReference(GV, *GV->getParent());
  67 }
  68
  69 unsigned char
  70 X86Subtarget::classifyLocalReference(const GlobalValue *GV) const {
  71   // If we're not PIC, it's not very interesting.
  72   if (!isPositionIndependent())
  73     return X86II::MO_NO_FLAG;
  74
  75   if (is64Bit()) {
  76     // 64-bit ELF PIC local references may use GOTOFF relocations.
  77     if (isTargetELF()) {
  78       switch (TM.getCodeModel()) {
  79       // 64-bit small code model is simple: All rip-relative.
  80       case CodeModel::Tiny:
  81         llvm_unreachable("Tiny codesize model not supported on X86");
  82       case CodeModel::Small:
  83       case CodeModel::Kernel:
  84         return X86II::MO_NO_FLAG;
  85
  86       // The large PIC code model uses GOTOFF.
  87       case CodeModel::Large:
  88         return X86II::MO_GOTOFF;
  89
  90       // Medium is a hybrid: RIP-rel for code, GOTOFF for DSO local data.
  91       case CodeModel::Medium:
  92         if (isa<Function>(GV))
  93           return X86II::MO_NO_FLAG; // All code is RIP-relative
  94         return X86II::MO_GOTOFF;    // Local symbols use GOTOFF.
  95       }
  96       llvm_unreachable("invalid code model");
  97     }
  98
  99     // Otherwise, this is either a RIP-relative reference or a 64-bit movabsq,
 100     // both of which use MO_NO_FLAG.
 101     return X86II::MO_NO_FLAG;
 102   }
 103
 104   // The COFF dynamic linker just patches the executable sections.
 105   if (isTargetCOFF())
 106     return X86II::MO_NO_FLAG;
 107
 108   if (isTargetDarwin()) {
 109     // 32 bit macho has no relocation for a-b if a is undefined, even if
 110     // b is in the section that is being relocated.
 111     // This means we have to use o load even for GVs that are known to be
 112     // local to the dso.
 113     if (GV && (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
 114       return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
 115
 116     return X86II::MO_PIC_BASE_OFFSET;
 117   }
 118
 119   return X86II::MO_GOTOFF;
 120 }
 121
 122 unsigned char X86Subtarget::classifyGlobalReference(const GlobalValue *GV,
 123                                                     const Module &M) const {
 124   // The static large model never uses stubs.
 125   if (TM.getCodeModel() == CodeModel::Large && !isPositionIndependent())
 126     return X86II::MO_NO_FLAG;
 127
 128   // Absolute symbols can be referenced directly.
 129   if (GV) {
 130     if (Optional<ConstantRange> CR = GV->getAbsoluteSymbolRange()) {
 131       // See if we can use the 8-bit immediate form. Note that some instructions
 132       // will sign extend the immediate operand, so to be conservative we only
 133       // accept the range [0,128).
 134       if (CR->getUnsignedMax().ult(128))
 135         return X86II::MO_ABS8;
 136       else
 137         return X86II::MO_NO_FLAG;
 138     }
 139   }
 140
 141   if (TM.shouldAssumeDSOLocal(M, GV))
 142     return classifyLocalReference(GV);
 143
 144   if (isTargetCOFF()) {
 145     if (GV->hasDLLImportStorageClass())
 146       return X86II::MO_DLLIMPORT;
 147     return X86II::MO_COFFSTUB;
 148   }
 149
 150   if (is64Bit()) {
 151     // ELF supports a large, truly PIC code model with non-PC relative GOT
 152     // references. Other object file formats do not. Use the no-flag, 64-bit
 153     // reference for them.
 154     if (TM.getCodeModel() == CodeModel::Large)
 155       return isTargetELF() ? X86II::MO_GOT : X86II::MO_NO_FLAG;
 156     return X86II::MO_GOTPCREL;
 157   }
 158
 159   if (isTargetDarwin()) {
 160     if (!isPositionIndependent())
 161       return X86II::MO_DARWIN_NONLAZY;
 162     return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
 163   }
 164
 165   return X86II::MO_GOT;
 166 }
 167
 168 unsigned char
 169 X86Subtarget::classifyGlobalFunctionReference(const GlobalValue *GV) const {
 170   return classifyGlobalFunctionReference(GV, *GV->getParent());
 171 }
 172
 173 unsigned char
 174 X86Subtarget::classifyGlobalFunctionReference(const GlobalValue *GV,
 175                                               const Module &M) const {
 176   if (TM.shouldAssumeDSOLocal(M, GV))
 177     return X86II::MO_NO_FLAG;
 178
 179   // Functions on COFF can be non-DSO local for two reasons:
 180   // - They are marked dllimport
 181   // - They are extern_weak, and a stub is needed
 182   if (isTargetCOFF()) {
 183     if (GV->hasDLLImportStorageClass())
 184       return X86II::MO_DLLIMPORT;
 185     return X86II::MO_COFFSTUB;
 186   }
 187
 188   const Function *F = dyn_cast_or_null<Function>(GV);
 189
 190   if (isTargetELF()) {
 191     if (is64Bit() && F && (CallingConv::X86_RegCall == F->getCallingConv()))
 192       // According to psABI, PLT stub clobbers XMM8-XMM15.
 193       // In Regcall calling convention those registers are used for passing
 194       // parameters. Thus we need to prevent lazy binding in Regcall.
 195       return X86II::MO_GOTPCREL;
 196     // If PLT must be avoided then the call should be via GOTPCREL.
 197     if (((F && F->hasFnAttribute(Attribute::NonLazyBind)) ||
 198          (!F && M.getRtLibUseGOT())) &&
 199         is64Bit())
 200        return X86II::MO_GOTPCREL;
 201     return X86II::MO_PLT;
 202   }
 203
 204   if (is64Bit()) {
 205     if (F && F->hasFnAttribute(Attribute::NonLazyBind))
 206       // If the function is marked as non-lazy, generate an indirect call
 207       // which loads from the GOT directly. This avoids runtime overhead
 208       // at the cost of eager binding (and one extra byte of encoding).
 209       return X86II::MO_GOTPCREL;
 210     return X86II::MO_NO_FLAG;
 211   }
 212
 213   return X86II::MO_NO_FLAG;
 214 }
 215
 216 /// Return true if the subtarget allows calls to immediate address.
 217 bool X86Subtarget::isLegalToCallImmediateAddr() const {
 218   // FIXME: I386 PE/COFF supports PC relative calls using IMAGE_REL_I386_REL32
 219   // but WinCOFFObjectWriter::RecordRelocation cannot emit them.  Once it does,
 220   // the following check for Win32 should be removed.
 221   if (In64BitMode || isTargetWin32())
 222     return false;
 223   return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
 224 }
 225
 226 void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
 227   std::string CPUName = CPU;
 228   if (CPUName.empty())
 229     CPUName = "generic";
 230
 231   std::string FullFS = FS;
 232   if (In64BitMode) {
 233     // SSE2 should default to enabled in 64-bit mode, but can be turned off
 234     // explicitly.
 235     if (!FullFS.empty())
 236       FullFS = "+sse2," + FullFS;
 237     else
 238       FullFS = "+sse2";
 239
 240     // If no CPU was specified, enable 64bit feature to satisy later check.
 241     if (CPUName == "generic") {
 242       if (!FullFS.empty())
 243         FullFS = "+64bit," + FullFS;
 244       else
 245         FullFS = "+64bit";
 246     }
 247   }
 248
 249   // LAHF/SAHF are always supported in non-64-bit mode.
 250   if (!In64BitMode) {
 251     if (!FullFS.empty())
 252       FullFS = "+sahf," + FullFS;
 253     else
 254       FullFS = "+sahf";
 255   }
 256
 257   // Parse features string and set the CPU.
 258   ParseSubtargetFeatures(CPUName, FullFS);
 259
 260   // All CPUs that implement SSE4.2 or SSE4A support unaligned accesses of
 261   // 16-bytes and under that are reasonably fast. These features were
 262   // introduced with Intel's Nehalem/Silvermont and AMD's Family10h
 263   // micro-architectures respectively.
 264   if (hasSSE42() || hasSSE4A())
 265     IsUAMem16Slow = false;
 266
 267   // It's important to keep the MCSubtargetInfo feature bits in sync with
 268   // target data structure which is shared with MC code emitter, etc.
 269   if (In64BitMode)
 270     ToggleFeature(X86::Mode64Bit);
 271   else if (In32BitMode)
 272     ToggleFeature(X86::Mode32Bit);
 273   else if (In16BitMode)
 274     ToggleFeature(X86::Mode16Bit);
 275   else
 276     llvm_unreachable("Not 16-bit, 32-bit or 64-bit mode!");
 277
 278   LLVM_DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
 279                     << ", 3DNowLevel " << X863DNowLevel << ", 64bit "
 280                     << HasX86_64 << "\n");
 281   if (In64BitMode && !HasX86_64)
 282     report_fatal_error("64-bit code requested on a subtarget that doesn't "
 283                        "support it!");
 284
 285   // Stack alignment is 16 bytes on Darwin, Linux, kFreeBSD and Solaris (both
 286   // 32 and 64 bit) and for all 64-bit targets.
 287   if (StackAlignOverride)
 288     stackAlignment = StackAlignOverride;
 289   else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
 290            isTargetKFreeBSD() || In64BitMode)
 291     stackAlignment = 16;
 292
 293   // Some CPUs have more overhead for gather. The specified overhead is relative
 294   // to the Load operation. "2" is the number provided by Intel architects. This
 295   // parameter is used for cost estimation of Gather Op and comparison with
 296   // other alternatives.
 297   // TODO: Remove the explicit hasAVX512()?, That would mean we would only
 298   // enable gather with a -march.
 299   if (hasAVX512() || (hasAVX2() && hasFastGather()))
 300     GatherOverhead = 2;
 301   if (hasAVX512())
 302     ScatterOverhead = 2;
 303
 304   // Consume the vector width attribute or apply any target specific limit.
 305   if (PreferVectorWidthOverride)
 306     PreferVectorWidth = PreferVectorWidthOverride;
 307   else if (Prefer256Bit)
 308     PreferVectorWidth = 256;
 309 }
 310
 311 X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU,
 312                                                             StringRef FS) {
 313   initSubtargetFeatures(CPU, FS);
 314   return *this;
 315 }
 316
 317 X86Subtarget::X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
 318                            const X86TargetMachine &TM,
 319                            unsigned StackAlignOverride,
 320                            unsigned PreferVectorWidthOverride,
 321                            unsigned RequiredVectorWidth)
 322     : X86GenSubtargetInfo(TT, CPU, FS),
 323       PICStyle(PICStyles::None), TM(TM), TargetTriple(TT),
 324       StackAlignOverride(StackAlignOverride),
 325       PreferVectorWidthOverride(PreferVectorWidthOverride),
 326       RequiredVectorWidth(RequiredVectorWidth),
 327       In64BitMode(TargetTriple.getArch() == Triple::x86_64),
 328       In32BitMode(TargetTriple.getArch() == Triple::x86 &&
 329                   TargetTriple.getEnvironment() != Triple::CODE16),
 330       In16BitMode(TargetTriple.getArch() == Triple::x86 &&
 331                   TargetTriple.getEnvironment() == Triple::CODE16),
 332       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
 333       FrameLowering(*this, getStackAlignment()) {
 334   // Determine the PICStyle based on the target selected.
 335   if (!isPositionIndependent())
 336     setPICStyle(PICStyles::None);
 337   else if (is64Bit())
 338     setPICStyle(PICStyles::RIPRel);
 339   else if (isTargetCOFF())
 340     setPICStyle(PICStyles::None);
 341   else if (isTargetDarwin())
 342     setPICStyle(PICStyles::StubPIC);
 343   else if (isTargetELF())
 344     setPICStyle(PICStyles::GOT);
 345
 346   CallLoweringInfo.reset(new X86CallLowering(*getTargetLowering()));
 347   Legalizer.reset(new X86LegalizerInfo(*this, TM));
 348
 349   auto *RBI = new X86RegisterBankInfo(*getRegisterInfo());
 350   RegBankInfo.reset(RBI);
 351   InstSelector.reset(createX86InstructionSelector(TM, *this, *RBI));
 352 }
 353
 354 const CallLowering *X86Subtarget::getCallLowering() const {
 355   return CallLoweringInfo.get();
 356 }
 357
 358 const InstructionSelector *X86Subtarget::getInstructionSelector() const {
 359   return InstSelector.get();
 360 }
 361
 362 const LegalizerInfo *X86Subtarget::getLegalizerInfo() const {
 363   return Legalizer.get();
 364 }
 365
 366 const RegisterBankInfo *X86Subtarget::getRegBankInfo() const {
 367   return RegBankInfo.get();
 368 }
 369
 370 bool X86Subtarget::enableEarlyIfConversion() const {
 371   return hasCMov() && X86EarlyIfConv;
 372 }
 373
 374 void X86Subtarget::getPostRAMutations(
 375     std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
 376   Mutations.push_back(createX86MacroFusionDAGMutation());
 377 }