lib/Target/AArch64/AArch64Subtarget.cpp

   1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements the AArch64 specific subclass of TargetSubtarget.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "AArch64Subtarget.h"
  14
  15 #include "AArch64.h"
  16 #include "AArch64CallLowering.h"
  17 #include "AArch64InstrInfo.h"
  18 #include "AArch64LegalizerInfo.h"
  19 #include "AArch64PBQPRegAlloc.h"
  20 #include "AArch64RegisterBankInfo.h"
  21 #include "AArch64TargetMachine.h"
  22 #include "MCTargetDesc/AArch64AddressingModes.h"
  23 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
  24 #include "llvm/CodeGen/MachineScheduler.h"
  25 #include "llvm/IR/GlobalValue.h"
  26 #include "llvm/Support/TargetParser.h"
  27
  28 using namespace llvm;
  29
  30 #define DEBUG_TYPE "aarch64-subtarget"
  31
  32 #define GET_SUBTARGETINFO_CTOR
  33 #define GET_SUBTARGETINFO_TARGET_DESC
  34 #include "AArch64GenSubtargetInfo.inc"
  35
  36 static cl::opt<bool>
  37 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
  38                      "converter pass"), cl::init(true), cl::Hidden);
  39
  40 // If OS supports TBI, use this flag to enable it.
  41 static cl::opt<bool>
  42 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
  43                          "an address is ignored"), cl::init(false), cl::Hidden);
  44
  45 static cl::opt<bool>
  46     UseNonLazyBind("aarch64-enable-nonlazybind",
  47                    cl::desc("Call nonlazybind functions via direct GOT load"),
  48                    cl::init(false), cl::Hidden);
  49
  50 AArch64Subtarget &
  51 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
  52                                                   StringRef CPUString) {
  53   // Determine default and user-specified characteristics
  54
  55   if (CPUString.empty())
  56     CPUString = "generic";
  57
  58   ParseSubtargetFeatures(CPUString, FS);
  59   initializeProperties();
  60
  61   return *this;
  62 }
  63
  64 void AArch64Subtarget::initializeProperties() {
  65   // Initialize CPU specific properties. We should add a tablegen feature for
  66   // this in the future so we can specify it together with the subtarget
  67   // features.
  68   switch (ARMProcFamily) {
  69   case Others:
  70     break;
  71   case CortexA35:
  72     break;
  73   case CortexA53:
  74     PrefFunctionLogAlignment = 3;
  75     break;
  76   case CortexA55:
  77     break;
  78   case CortexA57:
  79     MaxInterleaveFactor = 4;
  80     PrefFunctionLogAlignment = 4;
  81     break;
  82   case CortexA65:
  83     PrefFunctionLogAlignment = 3;
  84     break;
  85   case CortexA72:
  86   case CortexA73:
  87   case CortexA75:
  88   case CortexA76:
  89     PrefFunctionLogAlignment = 4;
  90     break;
  91   case Cyclone:
  92     CacheLineSize = 64;
  93     PrefetchDistance = 280;
  94     MinPrefetchStride = 2048;
  95     MaxPrefetchIterationsAhead = 3;
  96     break;
  97   case ExynosM1:
  98     MaxInterleaveFactor = 4;
  99     MaxJumpTableSize = 8;
 100     PrefFunctionLogAlignment = 4;
 101     PrefLoopLogAlignment = 3;
 102     break;
 103   case ExynosM3:
 104     MaxInterleaveFactor = 4;
 105     MaxJumpTableSize = 20;
 106     PrefFunctionLogAlignment = 5;
 107     PrefLoopLogAlignment = 4;
 108     break;
 109   case Falkor:
 110     MaxInterleaveFactor = 4;
 111     // FIXME: remove this to enable 64-bit SLP if performance looks good.
 112     MinVectorRegisterBitWidth = 128;
 113     CacheLineSize = 128;
 114     PrefetchDistance = 820;
 115     MinPrefetchStride = 2048;
 116     MaxPrefetchIterationsAhead = 8;
 117     break;
 118   case Kryo:
 119     MaxInterleaveFactor = 4;
 120     VectorInsertExtractBaseCost = 2;
 121     CacheLineSize = 128;
 122     PrefetchDistance = 740;
 123     MinPrefetchStride = 1024;
 124     MaxPrefetchIterationsAhead = 11;
 125     // FIXME: remove this to enable 64-bit SLP if performance looks good.
 126     MinVectorRegisterBitWidth = 128;
 127     break;
 128   case NeoverseE1:
 129     PrefFunctionLogAlignment = 3;
 130     break;
 131   case NeoverseN1:
 132     PrefFunctionLogAlignment = 4;
 133     break;
 134   case Saphira:
 135     MaxInterleaveFactor = 4;
 136     // FIXME: remove this to enable 64-bit SLP if performance looks good.
 137     MinVectorRegisterBitWidth = 128;
 138     break;
 139   case ThunderX2T99:
 140     CacheLineSize = 64;
 141     PrefFunctionLogAlignment = 3;
 142     PrefLoopLogAlignment = 2;
 143     MaxInterleaveFactor = 4;
 144     PrefetchDistance = 128;
 145     MinPrefetchStride = 1024;
 146     MaxPrefetchIterationsAhead = 4;
 147     // FIXME: remove this to enable 64-bit SLP if performance looks good.
 148     MinVectorRegisterBitWidth = 128;
 149     break;
 150   case ThunderX:
 151   case ThunderXT88:
 152   case ThunderXT81:
 153   case ThunderXT83:
 154     CacheLineSize = 128;
 155     PrefFunctionLogAlignment = 3;
 156     PrefLoopLogAlignment = 2;
 157     // FIXME: remove this to enable 64-bit SLP if performance looks good.
 158     MinVectorRegisterBitWidth = 128;
 159     break;
 160   case TSV110:
 161     CacheLineSize = 64;
 162     PrefFunctionLogAlignment = 4;
 163     PrefLoopLogAlignment = 2;
 164     break;
 165   }
 166 }
 167
 168 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
 169                                    const std::string &FS,
 170                                    const TargetMachine &TM, bool LittleEndian)
 171     : AArch64GenSubtargetInfo(TT, CPU, FS),
 172       ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
 173       CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
 174       IsLittle(LittleEndian),
 175       TargetTriple(TT), FrameLowering(),
 176       InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),
 177       TLInfo(TM, *this) {
 178   if (AArch64::isX18ReservedByDefault(TT))
 179     ReserveXRegister.set(18);
 180
 181   CallLoweringInfo.reset(new AArch64CallLowering(*getTargetLowering()));
 182   Legalizer.reset(new AArch64LegalizerInfo(*this));
 183
 184   auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
 185
 186   // FIXME: At this point, we can't rely on Subtarget having RBI.
 187   // It's awkward to mix passing RBI and the Subtarget; should we pass
 188   // TII/TRI as well?
 189   InstSelector.reset(createAArch64InstructionSelector(
 190       *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
 191
 192   RegBankInfo.reset(RBI);
 193 }
 194
 195 const CallLowering *AArch64Subtarget::getCallLowering() const {
 196   return CallLoweringInfo.get();
 197 }
 198
 199 InstructionSelector *AArch64Subtarget::getInstructionSelector() const {
 200   return InstSelector.get();
 201 }
 202
 203 const LegalizerInfo *AArch64Subtarget::getLegalizerInfo() const {
 204   return Legalizer.get();
 205 }
 206
 207 const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
 208   return RegBankInfo.get();
 209 }
 210
 211 /// Find the target operand flags that describe how a global value should be
 212 /// referenced for the current subtarget.
 213 unsigned
 214 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
 215                                           const TargetMachine &TM) const {
 216   // MachO large model always goes via a GOT, simply to get a single 8-byte
 217   // absolute relocation on all global addresses.
 218   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
 219     return AArch64II::MO_GOT;
 220
 221   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) {
 222     if (GV->hasDLLImportStorageClass())
 223       return AArch64II::MO_GOT | AArch64II::MO_DLLIMPORT;
 224     if (getTargetTriple().isOSWindows())
 225       return AArch64II::MO_GOT | AArch64II::MO_COFFSTUB;
 226     return AArch64II::MO_GOT;
 227   }
 228
 229   // The small code model's direct accesses use ADRP, which cannot
 230   // necessarily produce the value 0 (if the code is above 4GB).
 231   // Same for the tiny code model, where we have a pc relative LDR.
 232   if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
 233       GV->hasExternalWeakLinkage())
 234     return AArch64II::MO_GOT;
 235
 236   // References to tagged globals are marked with MO_NC | MO_TAGGED to indicate
 237   // that their nominal addresses are tagged and outside of the code model. In
 238   // AArch64ExpandPseudo::expandMI we emit an additional instruction to set the
 239   // tag if necessary based on MO_TAGGED.
 240   if (AllowTaggedGlobals && !isa<FunctionType>(GV->getValueType()))
 241     return AArch64II::MO_NC | AArch64II::MO_TAGGED;
 242
 243   return AArch64II::MO_NO_FLAG;
 244 }
 245
 246 unsigned AArch64Subtarget::classifyGlobalFunctionReference(
 247     const GlobalValue *GV, const TargetMachine &TM) const {
 248   // MachO large model always goes via a GOT, because we don't have the
 249   // relocations available to do anything else..
 250   if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
 251       !GV->hasInternalLinkage())
 252     return AArch64II::MO_GOT;
 253
 254   // NonLazyBind goes via GOT unless we know it's available locally.
 255   auto *F = dyn_cast<Function>(GV);
 256   if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
 257       !TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
 258     return AArch64II::MO_GOT;
 259
 260   return AArch64II::MO_NO_FLAG;
 261 }
 262
 263 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
 264                                            unsigned NumRegionInstrs) const {
 265   // LNT run (at least on Cyclone) showed reasonably significant gains for
 266   // bi-directional scheduling. 253.perlbmk.
 267   Policy.OnlyTopDown = false;
 268   Policy.OnlyBottomUp = false;
 269   // Enabling or Disabling the latency heuristic is a close call: It seems to
 270   // help nearly no benchmark on out-of-order architectures, on the other hand
 271   // it regresses register pressure on a few benchmarking.
 272   Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
 273 }
 274
 275 bool AArch64Subtarget::enableEarlyIfConversion() const {
 276   return EnableEarlyIfConvert;
 277 }
 278
 279 bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
 280   if (!UseAddressTopByteIgnored)
 281     return false;
 282
 283   if (TargetTriple.isiOS()) {
 284     unsigned Major, Minor, Micro;
 285     TargetTriple.getiOSVersion(Major, Minor, Micro);
 286     return Major >= 8;
 287   }
 288
 289   return false;
 290 }
 291
 292 std::unique_ptr<PBQPRAConstraint>
 293 AArch64Subtarget::getCustomPBQPConstraints() const {
 294   return balanceFPOps() ? std::make_unique<A57ChainingConstraint>() : nullptr;
 295 }
 296
 297 void AArch64Subtarget::mirFileLoaded(MachineFunction &MF) const {
 298   // We usually compute max call frame size after ISel. Do the computation now
 299   // if the .mir file didn't specify it. Note that this will probably give you
 300   // bogus values after PEI has eliminated the callframe setup/destroy pseudo
 301   // instructions, specify explicitly if you need it to be correct.
 302   MachineFrameInfo &MFI = MF.getFrameInfo();
 303   if (!MFI.isMaxCallFrameSizeComputed())
 304     MFI.computeMaxCallFrameSize(MF);
 305 }