lib/Target/ARM/ARMScheduleSwift.td

   1 //=- ARMScheduleSwift.td - Swift Scheduling Definitions -*- tablegen -*----===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the itinerary class data for the Swift processor..
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 // ===---------------------------------------------------------------------===//
  14 // This section contains legacy support for itineraries. This is
  15 // required until SD and PostRA schedulers are replaced by MachineScheduler.
  16
  17 def SW_DIS0 : FuncUnit;
  18 def SW_DIS1 : FuncUnit;
  19 def SW_DIS2 : FuncUnit;
  20
  21 def SW_ALU0 : FuncUnit;
  22 def SW_ALU1 : FuncUnit;
  23 def SW_LS   : FuncUnit;
  24 def SW_IDIV : FuncUnit;
  25 def SW_FDIV : FuncUnit;
  26
  27 // FIXME: Need bypasses.
  28 // FIXME: Model the multiple stages of IIC_iMOVix2, IIC_iMOVix2addpc, and
  29 //        IIC_iMOVix2ld better.
  30 // FIXME: Model the special immediate shifts that are not microcoded.
  31 // FIXME: Do we need to model the fact that uses of r15 in a micro-op force it
  32 //        to issue on pipe 1?
  33 // FIXME: Model the pipelined behavior of CMP / TST instructions.
  34 // FIXME: Better model the microcode stages of multiply instructions, especially
  35 //        conditional variants.
  36 // FIXME: Add preload instruction when it is documented.
  37 // FIXME: Model non-pipelined nature of FP div / sqrt unit.
  38
  39 // Swift machine model for scheduling and other instruction cost heuristics.
  40 def SwiftModel : SchedMachineModel {
  41   let IssueWidth = 3; // 3 micro-ops are dispatched per cycle.
  42   let MicroOpBufferSize = 45; // Based on NEON renamed registers.
  43   let LoadLatency = 3;
  44   let MispredictPenalty = 14; // A branch direction mispredict.
  45   let CompleteModel = 0;      // FIXME: Remove if all instructions are covered.
  46
  47   // FIXME: Remove when all errors have been fixed.
  48   let FullInstRWOverlapCheck = 0;
  49 }
  50
  51 // Swift predicates.
  52 def IsFastImmShiftSwiftPred : SchedPredicate<[{TII->isSwiftFastImmShift(MI)}]>;
  53
  54 // Swift resource mapping.
  55 let SchedModel = SwiftModel in {
  56   // Processor resources.
  57   def SwiftUnitP01 : ProcResource<2>; // ALU unit.
  58   def SwiftUnitP0 : ProcResource<1> { let Super = SwiftUnitP01; } // Mul unit.
  59   def SwiftUnitP1 : ProcResource<1> { let Super = SwiftUnitP01; } // Br unit.
  60   def SwiftUnitP2 : ProcResource<1>; // LS unit.
  61   def SwiftUnitDiv : ProcResource<1>;
  62
  63   // Generic resource requirements.
  64   def SwiftWriteP0OneCycle : SchedWriteRes<[SwiftUnitP0]>;
  65   def SwiftWriteP0TwoCycle : SchedWriteRes<[SwiftUnitP0]> { let Latency = 2; }
  66   def SwiftWriteP0FourCycle : SchedWriteRes<[SwiftUnitP0]> { let Latency = 4; }
  67   def SwiftWriteP0SixCycle : SchedWriteRes<[SwiftUnitP0]> { let Latency = 6; }
  68   def SwiftWriteP0P1FourCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP1]> {
  69     let Latency = 4;
  70   }
  71   def SwiftWriteP0P1SixCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP1]> {
  72     let Latency = 6;
  73   }
  74   def SwiftWriteP01OneCycle : SchedWriteRes<[SwiftUnitP01]>;
  75   def SwiftWriteP1TwoCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 2; }
  76   def SwiftWriteP1FourCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 4; }
  77   def SwiftWriteP1SixCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 6; }
  78   def SwiftWriteP1EightCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 8; }
  79   def SwiftWriteP1TwelveCyc : SchedWriteRes<[SwiftUnitP1]> { let Latency = 12; }
  80   def SwiftWriteP01OneCycle2x : WriteSequence<[SwiftWriteP01OneCycle], 2>;
  81   def SwiftWriteP01OneCycle3x : WriteSequence<[SwiftWriteP01OneCycle], 3>;
  82   def SwiftWriteP01TwoCycle : SchedWriteRes<[SwiftUnitP01]> { let Latency = 2; }
  83   def SwiftWriteP01ThreeCycleTwoUops : SchedWriteRes<[SwiftUnitP01,
  84                                                       SwiftUnitP01]> {
  85     let Latency = 3;
  86     let NumMicroOps = 2;
  87   }
  88   def SwiftWriteP0ThreeCycleThreeUops : SchedWriteRes<[SwiftUnitP0]> {
  89     let Latency = 3;
  90     let NumMicroOps = 3;
  91     let ResourceCycles = [3];
  92   }
  93   // Plain load without writeback.
  94   def SwiftWriteP2ThreeCycle : SchedWriteRes<[SwiftUnitP2]> {
  95     let Latency = 3;
  96   }
  97   def SwiftWriteP2FourCycle : SchedWriteRes<[SwiftUnitP2]> {
  98     let Latency = 4;
  99   }
 100   // A store does not write to a register.
 101   def SwiftWriteP2 : SchedWriteRes<[SwiftUnitP2]> {
 102     let Latency = 0;
 103   }
 104   foreach Num = 1-4 in {
 105     def SwiftWrite#Num#xP2 : WriteSequence<[SwiftWriteP2], Num>;
 106   }
 107   def SwiftWriteP01OneCycle2x_load : WriteSequence<[SwiftWriteP01OneCycle,
 108                                                     SwiftWriteP01OneCycle,
 109                                                     SwiftWriteP2ThreeCycle]>;
 110   // 4.2.4 Arithmetic and Logical.
 111   // ALU operation register shifted by immediate variant.
 112   def SwiftWriteALUsi : SchedWriteVariant<[
 113     // lsl #2, lsl #1, or lsr #1.
 114     SchedVar<IsFastImmShiftSwiftPred, [SwiftWriteP01TwoCycle]>,
 115     SchedVar<NoSchedPred,             [WriteALU]>
 116   ]>;
 117   def SwiftWriteALUsr : SchedWriteVariant<[
 118     SchedVar<IsPredicatedPred, [SwiftWriteP01ThreeCycleTwoUops]>,
 119     SchedVar<NoSchedPred,      [SwiftWriteP01TwoCycle]>
 120   ]>;
 121   def SwiftWriteALUSsr : SchedWriteVariant<[
 122     SchedVar<IsPredicatedPred, [SwiftWriteP0ThreeCycleThreeUops]>,
 123     SchedVar<NoSchedPred,      [SwiftWriteP01TwoCycle]>
 124   ]>;
 125   def SwiftReadAdvanceALUsr : SchedReadVariant<[
 126     SchedVar<IsPredicatedPred, [SchedReadAdvance<2>]>,
 127     SchedVar<NoSchedPred,      [NoReadAdvance]>
 128   ]>;
 129   // ADC,ADD,NEG,RSB,RSC,SBC,SUB,ADR
 130   // AND,BIC,EOR,ORN,ORR
 131   // CLZ,RBIT,REV,REV16,REVSH,PKH
 132   def : WriteRes<WriteALU, [SwiftUnitP01]>;
 133   def : SchedAlias<WriteALUsi, SwiftWriteALUsi>;
 134   def : SchedAlias<WriteALUsr, SwiftWriteALUsr>;
 135   def : SchedAlias<WriteALUSsr, SwiftWriteALUSsr>;
 136   def : ReadAdvance<ReadALU, 0>;
 137   def : SchedAlias<ReadALUsr, SwiftReadAdvanceALUsr>;
 138   def : SchedAlias<WriteLd, SwiftWriteP2ThreeCycle>;
 139   def : SchedAlias<WriteST, SwiftWriteP2>;
 140
 141
 142   def SwiftChooseShiftKindP01OneOrTwoCycle : SchedWriteVariant<[
 143     SchedVar<IsFastImmShiftSwiftPred, [SwiftWriteP01OneCycle]>,
 144     SchedVar<NoSchedPred,             [SwiftWriteP01TwoCycle]>
 145   ]>;
 146
 147   // 4.2.5 Integer comparison
 148   def : WriteRes<WriteCMP, [SwiftUnitP01]>;
 149   def : SchedAlias<WriteCMPsi, SwiftChooseShiftKindP01OneOrTwoCycle>;
 150   def : SchedAlias<WriteCMPsr, SwiftWriteP01TwoCycle>;
 151
 152   // 4.2.6 Shift, Move
 153   // Shift
 154   //  ASR,LSL,ROR,RRX
 155   //  MOV(register-shiftedregister)  MVN(register-shiftedregister)
 156   // Move
 157   //  MOV,MVN
 158   //  MOVT
 159   // Sign/Zero extension
 160   def : InstRW<[SwiftWriteP01OneCycle],
 161                (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
 162                           "t2SXTB", "t2SXTH", "t2SXTB16", "t2UXTB", "t2UXTH",
 163                           "t2UXTB16")>;
 164   // Pseudo instructions.
 165   def : InstRW<[SwiftWriteP01OneCycle2x],
 166         (instregex "MOVCCi32imm", "MOVi32imm", "t2MOVCCi32imm",
 167                    "t2MOVi32imm")>;
 168   def : InstRW<[SwiftWriteP01OneCycle3x],
 169         (instregex "MOV_ga_pcrel", "t2MOV_ga_pcrel", "t2MOVi16_ga_pcrel")>;
 170   def : InstRW<[SwiftWriteP01OneCycle2x_load],
 171         (instregex "MOV_ga_pcrel_ldr")>;
 172
 173   def SwiftWriteP0TwoCycleTwoUops : WriteSequence<[SwiftWriteP0OneCycle], 2>;
 174
 175   def SwiftPredP0OneOrTwoCycle : SchedWriteVariant<[
 176     SchedVar<IsPredicatedPred, [ SwiftWriteP0TwoCycleTwoUops ]>,
 177     SchedVar<NoSchedPred,     [ SwiftWriteP0OneCycle ]>
 178   ]>;
 179
 180   // 4.2.7 Select
 181   // SEL
 182   def : InstRW<[SwiftPredP0OneOrTwoCycle], (instregex "SEL", "t2SEL")>;
 183
 184   // 4.2.8 Bitfield
 185   // BFI,BFC, SBFX,UBFX
 186   def : InstRW< [SwiftWriteP01TwoCycle],
 187         (instregex "BFC", "BFI", "UBFX", "SBFX", "(t|t2)BFC", "(t|t2)BFI",
 188         "(t|t2)UBFX", "(t|t2)SBFX")>;
 189
 190   // 4.2.9 Saturating arithmetic
 191   def : InstRW< [SwiftWriteP01TwoCycle],
 192         (instregex "QADD", "QSUB", "QDADD", "QDSUB", "SSAT", "SSAT16", "USAT",
 193         "USAT16", "QADD8", "QADD16", "QSUB8", "QSUB16", "QASX", "QSAX",
 194         "UQADD8", "UQADD16","UQSUB8","UQSUB16","UQASX","UQSAX", "t2QADD",
 195         "t2QSUB", "t2QDADD", "t2QDSUB", "t2SSAT", "t2SSAT16", "t2USAT",
 196         "t2QADD8", "t2QADD16", "t2QSUB8", "t2QSUB16", "t2QASX", "t2QSAX",
 197         "t2UQADD8", "t2UQADD16","t2UQSUB8","t2UQSUB16","t2UQASX","t2UQSAX")>;
 198
 199   // 4.2.10 Parallel Arithmetic
 200   // Not flag setting.
 201   def : InstRW< [SwiftWriteALUsr],
 202         (instregex "SADD8", "SADD16", "SSUB8", "SSUB16", "SASX", "SSAX",
 203         "UADD8", "UADD16", "USUB8", "USUB16", "UASX", "USAX", "t2SADD8",
 204         "t2SADD16", "t2SSUB8", "t2SSUB16", "t2SASX", "t2SSAX", "t2UADD8",
 205         "t2UADD16", "t2USUB8", "t2USUB16", "t2UASX", "t2USAX")>;
 206   // Flag setting.
 207   def : InstRW< [SwiftWriteP01TwoCycle],
 208        (instregex "SHADD8", "SHADD16", "SHSUB8", "SHSUB16", "SHASX", "SHSAX",
 209        "SXTAB", "SXTAB16", "SXTAH", "UHADD8", "UHADD16", "UHSUB8", "UHSUB16",
 210        "UHASX", "UHSAX", "UXTAB", "UXTAB16", "UXTAH", "t2SHADD8", "t2SHADD16",
 211        "t2SHSUB8", "t2SHSUB16", "t2SHASX", "t2SHSAX", "t2SXTAB", "t2SXTAB16",
 212        "t2SXTAH", "t2UHADD8", "t2UHADD16", "t2UHSUB8", "t2UHSUB16", "t2UHASX",
 213        "t2UHSAX", "t2UXTAB", "t2UXTAB16", "t2UXTAH")>;
 214
 215   // 4.2.11 Sum of Absolute Difference
 216   def : InstRW< [SwiftWriteP0P1FourCycle], (instregex "USAD8") >;
 217   def : InstRW<[SwiftWriteP0P1FourCycle, ReadALU, ReadALU, SchedReadAdvance<2>],
 218         (instregex "USADA8")>;
 219
 220   // 4.2.12 Integer Multiply (32-bit result)
 221   // Two sources.
 222   def : InstRW< [SwiftWriteP0FourCycle],
 223         (instregex "MUL", "SMMUL", "SMMULR", "SMULBB", "SMULBT",
 224         "SMULTB", "SMULTT", "SMULWB", "SMULWT", "SMUSD", "SMUSDX", "t2MUL",
 225         "t2SMMUL", "t2SMMULR", "t2SMULBB", "t2SMULBT", "t2SMULTB", "t2SMULTT",
 226         "t2SMULWB", "t2SMULWT", "t2SMUSD")>;
 227
 228   def SwiftWriteP0P01FiveCycleTwoUops :
 229       SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]>  {
 230     let Latency = 5;
 231   }
 232
 233   def SwiftPredP0P01FourFiveCycle : SchedWriteVariant<[
 234     SchedVar<IsPredicatedPred, [ SwiftWriteP0P01FiveCycleTwoUops ]>,
 235     SchedVar<NoSchedPred,      [ SwiftWriteP0FourCycle ]>
 236   ]>;
 237
 238   def SwiftReadAdvanceFourCyclesPred : SchedReadVariant<[
 239      SchedVar<IsPredicatedPred, [SchedReadAdvance<4>]>,
 240      SchedVar<NoSchedPred,      [ReadALU]>
 241   ]>;
 242
 243   // Multiply accumulate, three sources
 244   def : InstRW< [SwiftPredP0P01FourFiveCycle, ReadALU, ReadALU,
 245                  SwiftReadAdvanceFourCyclesPred],
 246         (instregex "MLA", "MLS", "SMMLA", "SMMLAR", "SMMLS", "SMMLSR",
 247         "t2MLA", "t2MLS", "t2SMMLA", "t2SMMLAR", "t2SMMLS",
 248         "t2SMMLSR")>;
 249
 250   // 4.2.13 Integer Multiply (32-bit result, Q flag)
 251   def : InstRW< [SwiftWriteP0FourCycle],
 252         (instregex "SMUAD", "SMUADX", "t2SMUAD", "t2SMUADX")>;
 253   def : InstRW< [SwiftPredP0P01FourFiveCycle, ReadALU, ReadALU,
 254                  SwiftReadAdvanceFourCyclesPred],
 255         (instregex "SMLABB", "SMLABT", "SMLATB", "SMLATT", "SMLSD", "SMLSDX",
 256         "SMLAWB", "SMLAWT", "t2SMLABB", "t2SMLABT", "t2SMLATB", "t2SMLATT",
 257         "t2SMLSD", "t2SMLSDX", "t2SMLAWB", "t2SMLAWT")>;
 258   def : InstRW< [SwiftPredP0P01FourFiveCycle],
 259         (instregex "SMLAD", "SMLADX", "t2SMLAD", "t2SMLADX")>;
 260
 261   def SwiftP0P0P01FiveCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]> {
 262     let Latency = 5;
 263     let NumMicroOps = 3;
 264     let ResourceCycles = [2, 1];
 265   }
 266   def SwiftWrite1Cycle : SchedWriteRes<[]> {
 267     let Latency = 1;
 268     let NumMicroOps = 0;
 269   }
 270   def SwiftWrite5Cycle : SchedWriteRes<[]> {
 271     let Latency = 5;
 272     let NumMicroOps = 0;
 273   }
 274   def SwiftWrite6Cycle : SchedWriteRes<[]> {
 275     let Latency = 6;
 276     let NumMicroOps = 0;
 277   }
 278
 279   // 4.2.14 Integer Multiply, Long
 280   def : InstRW< [SwiftP0P0P01FiveCycle, SwiftWrite5Cycle],
 281         (instregex "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$")>;
 282
 283   def Swift2P03P01FiveCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]> {
 284     let Latency = 7;
 285     let NumMicroOps = 5;
 286     let ResourceCycles = [2, 3];
 287   }
 288
 289   // Aliasing sub-target specific WriteRes to generic ones
 290   def : SchedAlias<WriteMUL16, SwiftWriteP0FourCycle>;
 291   def : SchedAlias<WriteMUL32, SwiftWriteP0FourCycle>;
 292   def : SchedAlias<WriteMUL64Lo, SwiftP0P0P01FiveCycle>;
 293   def : SchedAlias<WriteMUL64Hi, SwiftWrite5Cycle>;
 294   def : SchedAlias<WriteMAC16, SwiftPredP0P01FourFiveCycle>;
 295   def : SchedAlias<WriteMAC32, SwiftPredP0P01FourFiveCycle>;
 296   def : SchedAlias<WriteMAC64Lo, SwiftWrite5Cycle>;
 297   def : SchedAlias<WriteMAC64Hi, Swift2P03P01FiveCycle>;
 298   def : ReadAdvance<ReadMUL, 0>;
 299   def : SchedAlias<ReadMAC, SwiftReadAdvanceFourCyclesPred>;
 300
 301   // 4.2.15 Integer Multiply Accumulate, Long
 302   // 4.2.16 Integer Multiply Accumulate, Dual
 303   // 4.2.17 Integer Multiply Accumulate Accumulate, Long
 304   // We are being a bit inaccurate here.
 305   def : InstRW< [SwiftWrite5Cycle, Swift2P03P01FiveCycle, ReadALU, ReadALU,
 306                  SchedReadAdvance<4>, SchedReadAdvance<3>],
 307         (instregex "SMLAL", "UMLAL", "SMLALBT",
 308         "SMLALTB", "SMLALTT", "SMLALD", "SMLALDX", "SMLSLD", "SMLSLDX",
 309         "UMAAL", "t2SMLAL", "t2UMLAL", "t2SMLALBB", "t2SMLALBT",
 310         "t2SMLALTB", "t2SMLALTT", "t2SMLALD", "t2SMLALDX", "t2SMLSLD", "t2SMLSLDX",
 311         "t2UMAAL")>;
 312
 313   def SwiftDiv : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
 314     let NumMicroOps = 1;
 315     let Latency = 14;
 316     let ResourceCycles = [1, 14];
 317   }
 318   // 4.2.18 Integer Divide
 319   def : WriteRes<WriteDIV, [SwiftUnitDiv]>; // Workaround.
 320   def : InstRW <[SwiftDiv],
 321         (instregex "SDIV", "UDIV", "t2SDIV", "t2UDIV")>;
 322
 323   // 4.2.19 Integer Load Single Element
 324   // 4.2.20 Integer Load Signextended
 325   def SwiftWriteP2P01ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> {
 326     let Latency = 3;
 327     let NumMicroOps = 2;
 328   }
 329   def SwiftWriteP2P01FourCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> {
 330     let Latency = 4;
 331     let NumMicroOps = 2;
 332   }
 333   def SwiftWriteP2P01P01FourCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01,
 334                                                    SwiftUnitP01]> {
 335     let Latency = 4;
 336     let NumMicroOps = 3;
 337   }
 338   def SwiftWriteP2P2ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP2]> {
 339     let Latency = 3;
 340     let NumMicroOps = 2;
 341   }
 342   def SwiftWriteP2P2P01ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP2,
 343                                                    SwiftUnitP01]> {
 344     let Latency = 3;
 345     let NumMicroOps = 3;
 346   }
 347   def SwiftWrBackOne : SchedWriteRes<[]> {
 348     let Latency = 1;
 349     let NumMicroOps = 0;
 350   }
 351   def SwiftWriteLdFour : SchedWriteRes<[]> {
 352     let Latency = 4;
 353     let NumMicroOps = 0;
 354   }
 355    // Not accurate.
 356   def : InstRW<[SwiftWriteP2ThreeCycle],
 357         (instregex "LDR(i12|rs)$", "LDRB(i12|rs)$", "t2LDR(i8|i12|s|pci)",
 358         "t2LDR(H|B)(i8|i12|s|pci)", "LDREX", "tLDR[BH](r|i|spi|pci|pciASM)",
 359         "tLDR(r|i|spi|pci|pciASM)")>;
 360   def : InstRW<[SwiftWriteP2ThreeCycle],
 361         (instregex "LDRH$",  "PICLDR$", "PICLDR(H|B)$", "LDRcp$")>;
 362   def : InstRW<[SwiftWriteP2P01FourCycle],
 363         (instregex "PICLDRS(H|B)$", "t2LDRS(H|B)(i|r|p|s)", "LDRS(H|B)$",
 364         "t2LDRpci_pic", "tLDRS(B|H)")>;
 365   def : InstRW<[SwiftWriteP2P01ThreeCycle,  SwiftWrBackOne],
 366         (instregex "LD(RB|R)(_|T_)(POST|PRE)_(IMM|REG)", "LDRH(_PRE|_POST)",
 367         "LDR(T|BT)_POST_(REG|IMM)", "LDRHT(i|r)",
 368         "t2LD(R|RB|RH)_(PRE|POST)", "t2LD(R|RB|RH)T")>;
 369   def : InstRW<[SwiftWriteP2P01P01FourCycle, SwiftWrBackOne],
 370         (instregex "LDR(SH|SB)(_POST|_PRE)", "t2LDR(SH|SB)(_POST|_PRE)",
 371         "LDRS(B|H)T(i|r)", "t2LDRS(B|H)T(i|r)?")>;
 372
 373   // 4.2.21 Integer Dual Load
 374   // Not accurate.
 375   def : InstRW<[SwiftWriteP2P2ThreeCycle, SwiftWriteLdFour],
 376         (instregex "t2LDRDi8", "LDRD$")>;
 377   def : InstRW<[SwiftWriteP2P2P01ThreeCycle, SwiftWriteLdFour, SwiftWrBackOne],
 378         (instregex "LDRD_(POST|PRE)", "t2LDRD_(POST|PRE)")>;
 379
 380   // 4.2.22 Integer Load, Multiple
 381   // NumReg = 1 .. 16
 382   foreach Lat = 3-25 in {
 383     def SwiftWriteLM#Lat#Cy : SchedWriteRes<[SwiftUnitP2]> {
 384       let Latency = Lat;
 385     }
 386     def SwiftWriteLM#Lat#CyNo : SchedWriteRes<[]> {
 387       let Latency = Lat;
 388       let NumMicroOps = 0;
 389     }
 390   }
 391   // Predicate.
 392   foreach NumAddr = 1-16 in {
 393     def SwiftLMAddr#NumAddr#Pred : SchedPredicate<"TII->getNumLDMAddresses(*MI) == "#NumAddr>;
 394   }
 395   def SwiftWriteLDMAddrNoWB : SchedWriteRes<[SwiftUnitP01]> { let Latency = 0; }
 396   def SwiftWriteLDMAddrWB : SchedWriteRes<[SwiftUnitP01, SwiftUnitP01]>;
 397   def SwiftWriteLM : SchedWriteVariant<[
 398     SchedVar<SwiftLMAddr2Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy]>,
 399     SchedVar<SwiftLMAddr3Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
 400                                 SwiftWriteLM5Cy]>,
 401     SchedVar<SwiftLMAddr4Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
 402                                 SwiftWriteLM5Cy, SwiftWriteLM6Cy]>,
 403     SchedVar<SwiftLMAddr5Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
 404                                 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
 405                                 SwiftWriteLM7Cy]>,
 406     SchedVar<SwiftLMAddr6Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
 407                                 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
 408                                 SwiftWriteLM7Cy, SwiftWriteLM8Cy]>,
 409     SchedVar<SwiftLMAddr7Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
 410                                 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
 411                                 SwiftWriteLM7Cy, SwiftWriteLM8Cy,
 412                                 SwiftWriteLM9Cy]>,
 413     SchedVar<SwiftLMAddr8Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
 414                                 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
 415                                 SwiftWriteLM7Cy, SwiftWriteLM8Cy,
 416                                 SwiftWriteLM9Cy, SwiftWriteLM10Cy]>,
 417     SchedVar<SwiftLMAddr9Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
 418                                 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
 419                                 SwiftWriteLM7Cy, SwiftWriteLM8Cy,
 420                                 SwiftWriteLM9Cy, SwiftWriteLM10Cy,
 421                                 SwiftWriteLM11Cy]>,
 422     SchedVar<SwiftLMAddr10Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
 423                                 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
 424                                 SwiftWriteLM7Cy, SwiftWriteLM8Cy,
 425                                 SwiftWriteLM9Cy, SwiftWriteLM10Cy,
 426                                 SwiftWriteLM11Cy, SwiftWriteLM12Cy]>,
 427     SchedVar<SwiftLMAddr11Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
 428                                 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
 429                                 SwiftWriteLM7Cy, SwiftWriteLM8Cy,
 430                                 SwiftWriteLM9Cy, SwiftWriteLM10Cy,
 431                                 SwiftWriteLM11Cy, SwiftWriteLM12Cy,
 432                                 SwiftWriteLM13Cy]>,
 433     SchedVar<SwiftLMAddr12Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
 434                                 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
 435                                 SwiftWriteLM7Cy, SwiftWriteLM8Cy,
 436                                 SwiftWriteLM9Cy, SwiftWriteLM10Cy,
 437                                 SwiftWriteLM11Cy, SwiftWriteLM12Cy,
 438                                 SwiftWriteLM13Cy, SwiftWriteLM14Cy]>,
 439     SchedVar<SwiftLMAddr13Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
 440                                 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
 441                                 SwiftWriteLM7Cy, SwiftWriteLM8Cy,
 442                                 SwiftWriteLM9Cy, SwiftWriteLM10Cy,
 443                                 SwiftWriteLM11Cy, SwiftWriteLM12Cy,
 444                                 SwiftWriteLM13Cy, SwiftWriteLM14Cy,
 445                                 SwiftWriteLM15Cy]>,
 446     SchedVar<SwiftLMAddr14Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
 447                                 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
 448                                 SwiftWriteLM7Cy, SwiftWriteLM8Cy,
 449                                 SwiftWriteLM9Cy, SwiftWriteLM10Cy,
 450                                 SwiftWriteLM11Cy, SwiftWriteLM12Cy,
 451                                 SwiftWriteLM13Cy, SwiftWriteLM14Cy,
 452                                 SwiftWriteLM15Cy, SwiftWriteLM16Cy]>,
 453     SchedVar<SwiftLMAddr15Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
 454                                 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
 455                                 SwiftWriteLM7Cy, SwiftWriteLM8Cy,
 456                                 SwiftWriteLM9Cy, SwiftWriteLM10Cy,
 457                                 SwiftWriteLM11Cy, SwiftWriteLM12Cy,
 458                                 SwiftWriteLM13Cy, SwiftWriteLM14Cy,
 459                                 SwiftWriteLM15Cy, SwiftWriteLM16Cy,
 460                                 SwiftWriteLM17Cy]>,
 461     SchedVar<SwiftLMAddr16Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy,
 462                                 SwiftWriteLM5Cy, SwiftWriteLM6Cy,
 463                                 SwiftWriteLM7Cy, SwiftWriteLM8Cy,
 464                                 SwiftWriteLM9Cy, SwiftWriteLM10Cy,
 465                                 SwiftWriteLM11Cy, SwiftWriteLM12Cy,
 466                                 SwiftWriteLM13Cy, SwiftWriteLM14Cy,
 467                                 SwiftWriteLM15Cy, SwiftWriteLM16Cy,
 468                                 SwiftWriteLM17Cy, SwiftWriteLM18Cy]>,
 469     // Unknow number of registers, just use resources for two registers.
 470     SchedVar<NoSchedPred,      [SwiftWriteLM3Cy, SwiftWriteLM4Cy,
 471                                 SwiftWriteLM5CyNo, SwiftWriteLM6CyNo,
 472                                 SwiftWriteLM7CyNo, SwiftWriteLM8CyNo,
 473                                 SwiftWriteLM9CyNo, SwiftWriteLM10CyNo,
 474                                 SwiftWriteLM11CyNo, SwiftWriteLM12CyNo,
 475                                 SwiftWriteLM13CyNo, SwiftWriteLM14CyNo,
 476                                 SwiftWriteLM15CyNo, SwiftWriteLM16CyNo,
 477                                 SwiftWriteLM17CyNo, SwiftWriteLM18CyNo]>
 478
 479   ]> { let Variadic=1; }
 480
 481   def : InstRW<[SwiftWriteLM, SwiftWriteLDMAddrNoWB],
 482         (instregex "LDM(IA|DA|DB|IB)$", "t2LDM(IA|DA|DB|IB)$",
 483         "(t|sys)LDM(IA|DA|DB|IB)$")>;
 484   def : InstRW<[SwiftWriteLDMAddrWB, SwiftWriteLM],
 485         (instregex /*"t2LDMIA_RET", "tLDMIA_RET", "LDMIA_RET",*/
 486         "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>;
 487   def : InstRW<[SwiftWriteLDMAddrWB, SwiftWriteLM, SwiftWriteP1TwoCycle],
 488         (instregex "LDMIA_RET", "(t|t2)LDMIA_RET", "tPOP")>;
 489   // 4.2.23 Integer Store, Single Element
 490   def : InstRW<[SwiftWriteP2],
 491         (instregex "PICSTR", "STR(i12|rs)", "STRB(i12|rs)", "STRH$", "STREX",
 492         "t2STR(i12|i8|s)$", "t2STR[BH](i12|i8|s)$", "tSTR[BH](i|r)", "tSTR(i|r)", "tSTRspi")>;
 493
 494   def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteP2],
 495         (instregex "STR(B_|_|BT_|T_)(PRE_IMM|PRE_REG|POST_REG|POST_IMM)",
 496         "STR(i|r)_preidx", "STRB(i|r)_preidx", "STRH_preidx", "STR(H_|HT_)(PRE|POST)",
 497         "STR(BT|HT|T)", "t2STR_(PRE|POST)", "t2STR[BH]_(PRE|POST)",
 498         "t2STR_preidx", "t2STR[BH]_preidx", "t2ST(RB|RH|R)T")>;
 499
 500   // 4.2.24 Integer Store, Dual
 501   def : InstRW<[SwiftWriteP2, SwiftWriteP2, SwiftWriteP01OneCycle],
 502         (instregex "STRD$", "t2STRDi8")>;
 503   def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteP2, SwiftWriteP2,
 504                 SwiftWriteP01OneCycle],
 505         (instregex "(t2|t)STRD_(POST|PRE)", "STRD_(POST|PRE)")>;
 506
 507   // 4.2.25 Integer Store, Multiple
 508   def SwiftWriteStIncAddr : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> {
 509     let Latency = 0;
 510     let NumMicroOps = 2;
 511   }
 512   foreach NumAddr = 1-16 in {
 513      def SwiftWriteSTM#NumAddr : WriteSequence<[SwiftWriteStIncAddr], NumAddr>;
 514   }
 515   def SwiftWriteSTM : SchedWriteVariant<[
 516     SchedVar<SwiftLMAddr2Pred, [SwiftWriteSTM2]>,
 517     SchedVar<SwiftLMAddr3Pred, [SwiftWriteSTM3]>,
 518     SchedVar<SwiftLMAddr4Pred, [SwiftWriteSTM4]>,
 519     SchedVar<SwiftLMAddr5Pred, [SwiftWriteSTM5]>,
 520     SchedVar<SwiftLMAddr6Pred, [SwiftWriteSTM6]>,
 521     SchedVar<SwiftLMAddr7Pred, [SwiftWriteSTM7]>,
 522     SchedVar<SwiftLMAddr8Pred, [SwiftWriteSTM8]>,
 523     SchedVar<SwiftLMAddr9Pred, [SwiftWriteSTM9]>,
 524     SchedVar<SwiftLMAddr10Pred,[SwiftWriteSTM10]>,
 525     SchedVar<SwiftLMAddr11Pred,[SwiftWriteSTM11]>,
 526     SchedVar<SwiftLMAddr12Pred,[SwiftWriteSTM12]>,
 527     SchedVar<SwiftLMAddr13Pred,[SwiftWriteSTM13]>,
 528     SchedVar<SwiftLMAddr14Pred,[SwiftWriteSTM14]>,
 529     SchedVar<SwiftLMAddr15Pred,[SwiftWriteSTM15]>,
 530     SchedVar<SwiftLMAddr16Pred,[SwiftWriteSTM16]>,
 531     // Unknow number of registers, just use resources for two registers.
 532     SchedVar<NoSchedPred,      [SwiftWriteSTM2]>
 533   ]>;
 534   def : InstRW<[SwiftWriteSTM],
 535         (instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>;
 536   def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteSTM],
 537         (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD",
 538         "tPUSH")>;
 539
 540   // LDRLIT pseudo instructions, they expand to LDR + PICADD
 541   def : InstRW<[SwiftWriteP2ThreeCycle, WriteALU],
 542         (instregex "t?LDRLIT_ga_abs", "t?LDRLIT_ga_pcrel")>;
 543   // LDRLIT_ga_pcrel_ldr expands to LDR + PICLDR
 544   def : InstRW<[SwiftWriteP2ThreeCycle, SwiftWriteP2ThreeCycle],
 545         (instregex "LDRLIT_ga_pcrel_ldr")>;
 546
 547   // 4.2.26 Branch
 548   def : WriteRes<WriteBr, [SwiftUnitP1]> { let Latency = 0; }
 549   def : WriteRes<WriteBrL, [SwiftUnitP1]> { let Latency = 2; }
 550   def : WriteRes<WriteBrTbl, [SwiftUnitP1, SwiftUnitP2]> { let Latency = 0; }
 551
 552   // 4.2.27 Not issued
 553   def : WriteRes<WriteNoop, []> { let Latency = 0; let NumMicroOps = 0; }
 554   def : InstRW<[WriteNoop], (instregex "t2IT", "IT")>;
 555
 556   // 4.2.28 Advanced SIMD, Integer, 2 cycle
 557   def : InstRW<[SwiftWriteP0TwoCycle],
 558         (instregex "VADDv", "VSUBv", "VNEG(s|f|v)", "VADDL", "VSUBL",
 559                    "VADDW", "VSUBW", "VHADD", "VHSUB", "VRHADD", "VPADDi",
 560                    "VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST",
 561                    "VSHL", "VSHR(s|u)", "VSHLL", "VQSHL(s|u)", "VBIF",
 562                    "VBIT", "VBSL", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>;
 563
 564   def : InstRW<[SwiftWriteP1TwoCycle],
 565         (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
 566
 567   // 4.2.29 Advanced SIMD, Integer, 4 cycle
 568   // 4.2.30 Advanced SIMD, Integer with Accumulate
 569   def : InstRW<[SwiftWriteP0FourCycle],
 570         (instregex "VABA", "VABAL", "VPADAL", "VRSRA", "VSRA", "VACGE", "VACGT",
 571         "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL",
 572         "VQRSHL", "VRSHR(u|s)", "VABS(f|v)", "VQABS", "VQNEG", "VQADD",
 573         "VQSUB")>;
 574   def : InstRW<[SwiftWriteP1FourCycle],
 575         (instregex "VRECPE", "VRSQRTE")>;
 576
 577   // 4.2.31 Advanced SIMD, Add and Shift with Narrow
 578   def : InstRW<[SwiftWriteP0P1FourCycle],
 579         (instregex "VADDHN", "VSUBHN", "VSHRN")>;
 580   def : InstRW<[SwiftWriteP0P1SixCycle],
 581         (instregex "VRADDHN", "VRSUBHN", "VRSHRN", "VQSHRN", "VQSHRUN",
 582                    "VQRSHRN", "VQRSHRUN")>;
 583
 584   // 4.2.32 Advanced SIMD, Vector Table Lookup
 585   foreach Num = 1-4 in {
 586     def SwiftWrite#Num#xP1TwoCycle : WriteSequence<[SwiftWriteP1TwoCycle], Num>;
 587   }
 588   def : InstRW<[SwiftWrite1xP1TwoCycle],
 589         (instregex "VTB(L|X)1")>;
 590   def : InstRW<[SwiftWrite2xP1TwoCycle],
 591         (instregex "VTB(L|X)2")>;
 592   def : InstRW<[SwiftWrite3xP1TwoCycle],
 593         (instregex "VTB(L|X)3")>;
 594   def : InstRW<[SwiftWrite4xP1TwoCycle],
 595         (instregex "VTB(L|X)4")>;
 596
 597   // 4.2.33 Advanced SIMD, Transpose
 598   def : InstRW<[SwiftWriteP1FourCycle, SwiftWriteP1FourCycle,
 599                 SwiftWriteP1TwoCycle/*RsrcOnly*/, SchedReadAdvance<2>],
 600         (instregex "VSWP", "VTRN", "VUZP", "VZIP")>;
 601
 602   // 4.2.34 Advanced SIMD and VFP, Floating Point
 603   def : InstRW<[SwiftWriteP0TwoCycle], (instregex "VABS(S|D)$", "VNEG(S|D)$")>;
 604   def : InstRW<[SwiftWriteP0FourCycle],
 605         (instregex "VCMP(D|S|ZD|ZS)$", "VCMPE(D|S|ZD|ZS)")>;
 606   def : InstRW<[SwiftWriteP0FourCycle],
 607         (instregex "VADD(S|f)", "VSUB(S|f)", "VABD", "VPADDf", "VMAX", "VMIN", "VPMAX",
 608                    "VPMIN")>;
 609   def : InstRW<[SwiftWriteP0SixCycle], (instregex "VADDD$", "VSUBD$")>;
 610   def : InstRW<[SwiftWriteP1EightCycle], (instregex "VRECPS", "VRSQRTS")>;
 611
 612   // 4.2.35 Advanced SIMD and VFP, Multiply
 613   def : InstRW<[SwiftWriteP1FourCycle],
 614         (instregex "VMUL(S|v|p|f|s)", "VNMULS", "VQDMULH", "VQRDMULH",
 615                    "VMULL", "VQDMULL")>;
 616   def : InstRW<[SwiftWriteP1FourCycle],
 617         (instregex "VMLA", "VMLS", "VNMLA", "VNMLS", "VFMA(S|D)", "VFMS(S|D)",
 618         "VFNMA", "VFNMS", "VMLAL", "VMLSL","VQDMLAL", "VQDMLSL")>;
 619   def : InstRW<[SwiftWriteP1EightCycle], (instregex "VFMAfd", "VFMSfd")>;
 620   def : InstRW<[SwiftWriteP1TwelveCyc], (instregex "VFMAfq", "VFMSfq")>;
 621
 622   // 4.2.36 Advanced SIMD and VFP, Convert
 623   def : InstRW<[SwiftWriteP1FourCycle], (instregex "VCVT", "V(S|U)IT", "VTO(S|U)")>;
 624
 625   // 4.2.37 Advanced SIMD and VFP, Move
 626   def : InstRW<[SwiftWriteP0TwoCycle],
 627         (instregex "VMOVv", "VMOV(S|D)$", "VMOV(S|D)cc",
 628                    "VMVNv", "VMVN(d|q)",
 629                    "FCONST(D|S)")>;
 630   def : InstRW<[SwiftWriteP1TwoCycle], (instregex "VMOVN", "VMOVL")>;
 631   def : InstRW<[WriteSequence<[SwiftWriteP0FourCycle, SwiftWriteP1TwoCycle]>],
 632         (instregex "VQMOVN")>;
 633   def : InstRW<[SwiftWriteP1TwoCycle], (instregex "VDUPLN")>;
 634   def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP1TwoCycle]>],
 635         (instregex "VDUP(8|16|32)")>;
 636   def : InstRW<[SwiftWriteP2ThreeCycle], (instregex "VMOVRS$")>;
 637   def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP0TwoCycle]>],
 638         (instregex "VMOVSR$", "VSETLN")>;
 639   def : InstRW<[SwiftWriteP2ThreeCycle, SwiftWriteP2FourCycle],
 640         (instregex "VMOVRR(D|S)$")>;
 641   def : InstRW<[SwiftWriteP2FourCycle], (instregex "VMOVDRR$")>;
 642   def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP1TwoCycle]>,
 643                 WriteSequence<[SwiftWrite1Cycle, SwiftWriteP2FourCycle,
 644                                SwiftWriteP1TwoCycle]>],
 645                 (instregex "VMOVSRR$")>;
 646   def : InstRW<[WriteSequence<[SwiftWriteP1TwoCycle, SwiftWriteP2ThreeCycle]>],
 647         (instregex "VGETLN(u|i)")>;
 648   def : InstRW<[WriteSequence<[SwiftWriteP1TwoCycle, SwiftWriteP2ThreeCycle,
 649                                SwiftWriteP01OneCycle]>],
 650         (instregex "VGETLNs")>;
 651
 652   // 4.2.38 Advanced SIMD and VFP, Move FPSCR
 653   // Serializing instructions.
 654   def SwiftWaitP0For15Cy : SchedWriteRes<[SwiftUnitP0]> {
 655     let Latency = 15;
 656     let ResourceCycles = [15];
 657   }
 658   def SwiftWaitP1For15Cy : SchedWriteRes<[SwiftUnitP1]> {
 659     let Latency = 15;
 660     let ResourceCycles = [15];
 661   }
 662   def SwiftWaitP2For15Cy : SchedWriteRes<[SwiftUnitP2]> {
 663     let Latency = 15;
 664     let ResourceCycles = [15];
 665   }
 666   def : InstRW<[SwiftWaitP0For15Cy, SwiftWaitP1For15Cy, SwiftWaitP2For15Cy],
 667         (instregex "VMRS")>;
 668   def : InstRW<[SwiftWaitP0For15Cy, SwiftWaitP1For15Cy, SwiftWaitP2For15Cy],
 669         (instregex "VMSR")>;
 670   // Not serializing.
 671   def : InstRW<[SwiftWriteP0TwoCycle], (instregex "FMSTAT")>;
 672
 673   // 4.2.39 Advanced SIMD and VFP, Load Single Element
 674   def : InstRW<[SwiftWriteLM4Cy], (instregex "VLDRD$", "VLDRS$")>;
 675
 676   // 4.2.40 Advanced SIMD and VFP, Store Single Element
 677   def : InstRW<[SwiftWriteLM4Cy], (instregex "VSTRD$", "VSTRS$")>;
 678
 679   // 4.2.41 Advanced SIMD and VFP, Load Multiple
 680   // 4.2.42 Advanced SIMD and VFP, Store Multiple
 681
 682   // Resource requirement for permuting, just reserves the resources.
 683   foreach Num = 1-28 in {
 684     def SwiftVLDMPerm#Num : SchedWriteRes<[SwiftUnitP1]> {
 685       let Latency = 0;
 686       let NumMicroOps = Num;
 687       let ResourceCycles = [Num];
 688     }
 689   }
 690
 691   // Pre RA pseudos - load/store to a Q register as a D register pair.
 692   def : InstRW<[SwiftWriteLM4Cy], (instregex "VLDMQIA$", "VSTMQIA$")>;
 693
 694   // Post RA not modelled accurately. We assume that register use of width 64
 695   // bit maps to a D register, 128 maps to a Q register. Not all different kinds
 696   // are accurately represented.
 697   def SwiftWriteVLDM : SchedWriteVariant<[
 698     // Load of one S register.
 699     SchedVar<SwiftLMAddr1Pred, [SwiftWriteLM4Cy]>,
 700     // Load of one D register.
 701     SchedVar<SwiftLMAddr2Pred, [SwiftWriteLM4Cy, SwiftWriteLM4CyNo]>,
 702     // Load of 3 S register.
 703     SchedVar<SwiftLMAddr3Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy,
 704                                 SwiftWriteLM13CyNo, SwiftWriteP01OneCycle,
 705                                 SwiftVLDMPerm3]>,
 706     // Load of a Q register (not necessarily true). We should not be mapping to
 707     // 4 S registers, either.
 708     SchedVar<SwiftLMAddr4Pred, [SwiftWriteLM4Cy, SwiftWriteLM4CyNo,
 709                                 SwiftWriteLM4CyNo, SwiftWriteLM4CyNo]>,
 710     // Load of 5 S registers.
 711     SchedVar<SwiftLMAddr5Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy,
 712                                 SwiftWriteLM13CyNo, SwiftWriteLM14CyNo,
 713                                 SwiftWriteLM17CyNo,  SwiftWriteP01OneCycle,
 714                                 SwiftVLDMPerm5]>,
 715     // Load of 3 D registers. (Must also be able to handle s register list -
 716     // though, not accurate)
 717     SchedVar<SwiftLMAddr6Pred, [SwiftWriteLM7Cy, SwiftWriteLM8Cy,
 718                                 SwiftWriteLM10Cy, SwiftWriteLM14CyNo,
 719                                 SwiftWriteLM14CyNo, SwiftWriteLM14CyNo,
 720                                 SwiftWriteP01OneCycle, SwiftVLDMPerm5]>,
 721     // Load of 7 S registers.
 722     SchedVar<SwiftLMAddr7Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy,
 723                                 SwiftWriteLM13Cy, SwiftWriteLM14CyNo,
 724                                 SwiftWriteLM17CyNo, SwiftWriteLM18CyNo,
 725                                 SwiftWriteLM21CyNo, SwiftWriteP01OneCycle,
 726                                 SwiftVLDMPerm7]>,
 727     // Load of two Q registers.
 728     SchedVar<SwiftLMAddr8Pred, [SwiftWriteLM7Cy, SwiftWriteLM8Cy,
 729                                 SwiftWriteLM13Cy, SwiftWriteLM13CyNo,
 730                                 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
 731                                 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
 732                                 SwiftWriteP01OneCycle,  SwiftVLDMPerm2]>,
 733     // Load of 9 S registers.
 734     SchedVar<SwiftLMAddr9Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy,
 735                                 SwiftWriteLM13Cy, SwiftWriteLM14CyNo,
 736                                 SwiftWriteLM17CyNo, SwiftWriteLM18CyNo,
 737                                 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
 738                                 SwiftWriteLM25CyNo, SwiftWriteP01OneCycle,
 739                                 SwiftVLDMPerm9]>,
 740     // Load of 5 D registers.
 741     SchedVar<SwiftLMAddr10Pred,[SwiftWriteLM7Cy, SwiftWriteLM8Cy,
 742                                 SwiftWriteLM10Cy, SwiftWriteLM14Cy,
 743                                 SwiftWriteLM14CyNo, SwiftWriteLM14CyNo,
 744                                 SwiftWriteLM14CyNo, SwiftWriteLM14CyNo,
 745                                 SwiftWriteLM14CyNo,  SwiftWriteLM14CyNo,
 746                                 SwiftWriteP01OneCycle, SwiftVLDMPerm5]>,
 747     // Inaccurate: reuse describtion from 9 S registers.
 748     SchedVar<SwiftLMAddr11Pred,[SwiftWriteLM9Cy, SwiftWriteLM10Cy,
 749                                 SwiftWriteLM13Cy, SwiftWriteLM14CyNo,
 750                                 SwiftWriteLM17CyNo, SwiftWriteLM18CyNo,
 751                                 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
 752                                 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
 753                                 SwiftWriteLM25CyNo, SwiftWriteP01OneCycle,
 754                                 SwiftVLDMPerm9]>,
 755     // Load of three Q registers.
 756     SchedVar<SwiftLMAddr12Pred,[SwiftWriteLM7Cy, SwiftWriteLM8Cy,
 757                                 SwiftWriteLM11Cy, SwiftWriteLM11Cy,
 758                                 SwiftWriteLM11CyNo, SwiftWriteLM11CyNo,
 759                                 SwiftWriteLM11CyNo, SwiftWriteLM11CyNo,
 760                                 SwiftWriteLM11CyNo, SwiftWriteLM11CyNo,
 761                                 SwiftWriteLM11CyNo, SwiftWriteLM11CyNo,
 762                                 SwiftWriteP01OneCycle, SwiftVLDMPerm3]>,
 763     // Inaccurate: reuse describtion from 9 S registers.
 764     SchedVar<SwiftLMAddr13Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy,
 765                                 SwiftWriteLM13Cy, SwiftWriteLM14CyNo,
 766                                 SwiftWriteLM17CyNo, SwiftWriteLM18CyNo,
 767                                 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
 768                                 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
 769                                 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
 770                                 SwiftWriteLM25CyNo, SwiftWriteP01OneCycle,
 771                                 SwiftVLDMPerm9]>,
 772     // Load of 7 D registers inaccurate.
 773     SchedVar<SwiftLMAddr14Pred,[SwiftWriteLM7Cy, SwiftWriteLM8Cy,
 774                                 SwiftWriteLM10Cy, SwiftWriteLM14Cy,
 775                                 SwiftWriteLM14Cy, SwiftWriteLM14CyNo,
 776                                 SwiftWriteLM14CyNo, SwiftWriteLM14CyNo,
 777                                 SwiftWriteLM14CyNo,  SwiftWriteLM14CyNo,
 778                                 SwiftWriteLM14CyNo,  SwiftWriteLM14CyNo,
 779                                 SwiftWriteP01OneCycle, SwiftVLDMPerm7]>,
 780     SchedVar<SwiftLMAddr15Pred,[SwiftWriteLM9Cy, SwiftWriteLM10Cy,
 781                                 SwiftWriteLM13Cy, SwiftWriteLM14Cy,
 782                                 SwiftWriteLM17Cy, SwiftWriteLM18CyNo,
 783                                 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
 784                                 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
 785                                 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
 786                                 SwiftWriteLM21CyNo, SwiftWriteLM22CyNo,
 787                                 SwiftWriteLM25CyNo, SwiftWriteP01OneCycle,
 788                                 SwiftVLDMPerm9]>,
 789     // Load of 4 Q registers.
 790     SchedVar<SwiftLMAddr16Pred,[SwiftWriteLM7Cy, SwiftWriteLM10Cy,
 791                                 SwiftWriteLM11Cy, SwiftWriteLM14Cy,
 792                                 SwiftWriteLM15Cy, SwiftWriteLM18CyNo,
 793                                 SwiftWriteLM19CyNo, SwiftWriteLM22CyNo,
 794                                 SwiftWriteLM19CyNo, SwiftWriteLM22CyNo,
 795                                 SwiftWriteLM19CyNo, SwiftWriteLM22CyNo,
 796                                 SwiftWriteLM19CyNo, SwiftWriteLM22CyNo,
 797                                 SwiftWriteLM19CyNo, SwiftWriteLM22CyNo,
 798                                 SwiftWriteP01OneCycle, SwiftVLDMPerm4]>,
 799     // Unknow number of registers, just use resources for two registers.
 800     SchedVar<NoSchedPred,      [SwiftWriteLM7Cy, SwiftWriteLM8Cy,
 801                                 SwiftWriteLM13Cy, SwiftWriteLM13CyNo,
 802                                 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
 803                                 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
 804                                 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
 805                                 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
 806                                 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
 807                                 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
 808                                 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
 809                                 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
 810                                 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
 811                                 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
 812                                 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
 813                                 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
 814                                 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
 815                                 SwiftWriteLM13CyNo, SwiftWriteLM13CyNo,
 816                                 SwiftWriteP01OneCycle,  SwiftVLDMPerm2]>
 817   ]> { let Variadic = 1; }
 818
 819   def : InstRW<[SwiftWriteVLDM], (instregex "VLDM[SD](IA|DB)$")>;
 820
 821   def : InstRW<[SwiftWriteP01OneCycle2x, SwiftWriteVLDM],
 822         (instregex "VLDM[SD](IA|DB)_UPD$")>;
 823
 824   def SwiftWriteVSTM : SchedWriteVariant<[
 825     // One S register.
 826     SchedVar<SwiftLMAddr1Pred, [SwiftWriteSTM1]>,
 827     // One D register.
 828     SchedVar<SwiftLMAddr2Pred, [SwiftWriteSTM1]>,
 829     // Three S registers.
 830     SchedVar<SwiftLMAddr3Pred, [SwiftWriteSTM4]>,
 831     // Assume one Q register.
 832     SchedVar<SwiftLMAddr4Pred, [SwiftWriteSTM1]>,
 833     SchedVar<SwiftLMAddr5Pred, [SwiftWriteSTM6]>,
 834     // Assume three D registers.
 835     SchedVar<SwiftLMAddr6Pred, [SwiftWriteSTM4]>,
 836     SchedVar<SwiftLMAddr7Pred, [SwiftWriteSTM8]>,
 837     // Assume two Q registers.
 838     SchedVar<SwiftLMAddr8Pred, [SwiftWriteSTM3]>,
 839     SchedVar<SwiftLMAddr9Pred, [SwiftWriteSTM10]>,
 840     // Assume 5 D registers.
 841     SchedVar<SwiftLMAddr10Pred, [SwiftWriteSTM6]>,
 842     SchedVar<SwiftLMAddr11Pred, [SwiftWriteSTM12]>,
 843     // Assume three Q registers.
 844     SchedVar<SwiftLMAddr12Pred, [SwiftWriteSTM4]>,
 845     SchedVar<SwiftLMAddr13Pred, [SwiftWriteSTM14]>,
 846     // Assume 7 D registers.
 847     SchedVar<SwiftLMAddr14Pred, [SwiftWriteSTM8]>,
 848     SchedVar<SwiftLMAddr15Pred, [SwiftWriteSTM16]>,
 849     // Assume four Q registers.
 850     SchedVar<SwiftLMAddr16Pred, [SwiftWriteSTM5]>,
 851     // Asumme two Q registers.
 852     SchedVar<NoSchedPred, [SwiftWriteSTM3]>
 853   ]> { let Variadic = 1; }
 854
 855   def : InstRW<[SwiftWriteVSTM], (instregex "VSTM[SD](IA|DB)$")>;
 856
 857   def : InstRW<[SwiftWriteP01OneCycle2x, SwiftWriteVSTM],
 858         (instregex "VSTM[SD](IA|DB)_UPD")>;
 859
 860   // 4.2.43 Advanced SIMD, Element or Structure Load and Store
 861   def SwiftWrite2xP2FourCy : SchedWriteRes<[SwiftUnitP2]> {
 862       let Latency = 4;
 863       let ResourceCycles = [2];
 864   }
 865   def SwiftWrite3xP2FourCy : SchedWriteRes<[SwiftUnitP2]> {
 866       let Latency = 4;
 867       let ResourceCycles = [3];
 868   }
 869   foreach Num = 1-2 in {
 870     def SwiftExt#Num#xP0 : SchedWriteRes<[SwiftUnitP0]> {
 871       let Latency = 0;
 872       let NumMicroOps = Num;
 873       let ResourceCycles = [Num];
 874     }
 875   }
 876   // VLDx
 877   // Multiple structures.
 878   // Single element structure loads.
 879   // We assume aligned.
 880   // Single/two register.
 881   def : InstRW<[SwiftWriteLM4Cy], (instregex "VLD1(d|q)(8|16|32|64)$")>;
 882   def : InstRW<[SwiftWriteLM4Cy, SwiftWriteP01OneCycle],
 883         (instregex "VLD1(d|q)(8|16|32|64)wb")>;
 884   // Three register.
 885   def : InstRW<[SwiftWrite3xP2FourCy],
 886         (instregex "VLD1(d|q)(8|16|32|64)T$", "VLD1d64TPseudo")>;
 887   def : InstRW<[SwiftWrite3xP2FourCy, SwiftWriteP01OneCycle],
 888         (instregex "VLD1(d|q)(8|16|32|64)Twb")>;
 889   /// Four Register.
 890   def : InstRW<[SwiftWrite2xP2FourCy],
 891         (instregex "VLD1(d|q)(8|16|32|64)Q$", "VLD1d64QPseudo")>;
 892   def : InstRW<[SwiftWrite2xP2FourCy, SwiftWriteP01OneCycle],
 893         (instregex "VLD1(d|q)(8|16|32|64)Qwb")>;
 894   // Two element structure loads.
 895   // Two/four register.
 896   def : InstRW<[SwiftWriteLM9Cy, SwiftExt2xP0, SwiftVLDMPerm2],
 897         (instregex "VLD2(d|q|b)(8|16|32)$", "VLD2q(8|16|32)Pseudo$")>;
 898   def : InstRW<[SwiftWriteLM9Cy, SwiftWriteP01OneCycle, SwiftExt2xP0,
 899                 SwiftVLDMPerm2],
 900         (instregex "VLD2(d|q|b)(8|16|32)wb", "VLD2q(8|16|32)PseudoWB")>;
 901   // Three element structure.
 902   def : InstRW<[SwiftWriteLM9Cy, SwiftWriteLM9CyNo, SwiftWriteLM9CyNo,
 903                 SwiftVLDMPerm3, SwiftWrite3xP2FourCy],
 904         (instregex "VLD3(d|q)(8|16|32)$")>;
 905   def : InstRW<[SwiftWriteLM9Cy, SwiftVLDMPerm3, SwiftWrite3xP2FourCy],
 906         (instregex "VLD3(d|q)(8|16|32)(oddP|P)seudo$")>;
 907
 908   def : InstRW<[SwiftWriteLM9Cy, SwiftWriteLM9CyNo, SwiftWriteLM9CyNo,
 909                 SwiftWriteP01OneCycle, SwiftVLDMPerm3, SwiftWrite3xP2FourCy],
 910         (instregex "VLD3(d|q)(8|16|32)_UPD$")>;
 911   def : InstRW<[SwiftWriteLM9Cy, SwiftWriteP01OneCycle, SwiftVLDMPerm3,
 912                 SwiftWrite3xP2FourCy],
 913         (instregex "VLD3(d|q)(8|16|32)(oddP|P)seudo_UPD")>;
 914   // Four element structure loads.
 915   def : InstRW<[SwiftWriteLM11Cy, SwiftWriteLM11Cy, SwiftWriteLM11Cy,
 916                 SwiftWriteLM11Cy, SwiftExt2xP0, SwiftVLDMPerm4,
 917                 SwiftWrite3xP2FourCy],
 918         (instregex "VLD4(d|q)(8|16|32)$")>;
 919   def : InstRW<[SwiftWriteLM11Cy,  SwiftExt2xP0, SwiftVLDMPerm4,
 920                 SwiftWrite3xP2FourCy],
 921         (instregex "VLD4(d|q)(8|16|32)(oddP|P)seudo$")>;
 922   def : InstRW<[SwiftWriteLM11Cy, SwiftWriteLM11Cy, SwiftWriteLM11Cy,
 923                 SwiftWriteLM11Cy, SwiftWriteP01OneCycle, SwiftExt2xP0,
 924                 SwiftVLDMPerm4, SwiftWrite3xP2FourCy],
 925         (instregex "VLD4(d|q)(8|16|32)_UPD")>;
 926   def : InstRW<[SwiftWriteLM11Cy, SwiftWriteP01OneCycle, SwiftExt2xP0,
 927                 SwiftVLDMPerm4, SwiftWrite3xP2FourCy],
 928         (instregex  "VLD4(d|q)(8|16|32)(oddP|P)seudo_UPD")>;
 929
 930   // Single all/lane loads.
 931   // One element structure.
 932   def : InstRW<[SwiftWriteLM6Cy, SwiftVLDMPerm2],
 933         (instregex "VLD1(LN|DUP)(d|q)(8|16|32)$", "VLD1(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
 934   def : InstRW<[SwiftWriteLM6Cy, SwiftWriteP01OneCycle, SwiftVLDMPerm2],
 935         (instregex "VLD1(LN|DUP)(d|q)(8|16|32)(wb|_UPD)",
 936                   "VLD1LNq(8|16|32)Pseudo_UPD")>;
 937   // Two element structure.
 938   def : InstRW<[SwiftWriteLM6Cy, SwiftWriteLM6Cy, SwiftExt1xP0, SwiftVLDMPerm2],
 939         (instregex "VLD2(DUP|LN)(d|q)(8|16|32|8x2|16x2|32x2)$",
 940                    "VLD2LN(d|q)(8|16|32)Pseudo$")>;
 941   def : InstRW<[SwiftWriteLM6Cy, SwiftWriteLM6Cy, SwiftWriteP01OneCycle,
 942                 SwiftExt1xP0, SwiftVLDMPerm2],
 943         (instregex "VLD2LN(d|q)(8|16|32)_UPD$")>;
 944   def : InstRW<[SwiftWriteLM6Cy, SwiftWriteP01OneCycle, SwiftWriteLM6Cy,
 945                 SwiftExt1xP0, SwiftVLDMPerm2],
 946         (instregex "VLD2DUPd(8|16|32|8x2|16x2|32x2)wb")>;
 947   def : InstRW<[SwiftWriteLM6Cy, SwiftWriteP01OneCycle, SwiftWriteLM6Cy,
 948                 SwiftExt1xP0, SwiftVLDMPerm2],
 949         (instregex "VLD2LN(d|q)(8|16|32)Pseudo_UPD")>;
 950   // Three element structure.
 951   def : InstRW<[SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM8Cy, SwiftExt1xP0,
 952                 SwiftVLDMPerm3],
 953         (instregex "VLD3(DUP|LN)(d|q)(8|16|32)$",
 954                    "VLD3(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
 955   def : InstRW<[SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM8Cy,
 956                 SwiftWriteP01OneCycle, SwiftExt1xP0, SwiftVLDMPerm3],
 957         (instregex "VLD3(LN|DUP)(d|q)(8|16|32)_UPD")>;
 958   def : InstRW<[SwiftWriteLM7Cy, SwiftWriteP01OneCycle, SwiftWriteLM8Cy,
 959                 SwiftWriteLM8Cy, SwiftExt1xP0, SwiftVLDMPerm3],
 960         (instregex "VLD3(LN|DUP)(d|q)(8|16|32)Pseudo_UPD")>;
 961   // Four element struture.
 962   def : InstRW<[SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10CyNo,
 963                 SwiftWriteLM10CyNo, SwiftExt1xP0, SwiftVLDMPerm5],
 964         (instregex "VLD4(LN|DUP)(d|q)(8|16|32)$",
 965                    "VLD4(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
 966   def : InstRW<[SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10CyNo,
 967                 SwiftWriteLM10CyNo, SwiftWriteP01OneCycle, SwiftExt1xP0,
 968                 SwiftVLDMPerm5],
 969         (instregex "VLD4(DUP|LN)(d|q)(8|16|32)_UPD")>;
 970   def : InstRW<[SwiftWriteLM8Cy, SwiftWriteP01OneCycle, SwiftWriteLM9Cy,
 971                 SwiftWriteLM10CyNo, SwiftWriteLM10CyNo, SwiftExt1xP0,
 972                 SwiftVLDMPerm5],
 973         (instregex "VLD4(DUP|LN)(d|q)(8|16|32)Pseudo_UPD")>;
 974   // VSTx
 975   // Multiple structures.
 976   // Single element structure store.
 977   def : InstRW<[SwiftWrite1xP2], (instregex "VST1d(8|16|32|64)$")>;
 978   def : InstRW<[SwiftWrite2xP2], (instregex "VST1q(8|16|32|64)$")>;
 979   def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2],
 980         (instregex "VST1d(8|16|32|64)wb")>;
 981   def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite2xP2],
 982         (instregex "VST1q(8|16|32|64)wb")>;
 983   def : InstRW<[SwiftWrite3xP2],
 984         (instregex "VST1d(8|16|32|64)T$", "VST1d64TPseudo$")>;
 985   def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite3xP2],
 986         (instregex "VST1d(8|16|32|64)Twb", "VST1d64TPseudoWB")>;
 987   def : InstRW<[SwiftWrite4xP2],
 988         (instregex "VST1d(8|16|32|64)(Q|QPseudo)$")>;
 989   def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2],
 990         (instregex "VST1d(8|16|32|64)(Qwb|QPseudoWB)")>;
 991   // Two element structure store.
 992   def : InstRW<[SwiftWrite1xP2, SwiftVLDMPerm1],
 993         (instregex "VST2(d|b)(8|16|32)$")>;
 994   def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2, SwiftVLDMPerm1],
 995         (instregex "VST2(b|d)(8|16|32)wb")>;
 996   def : InstRW<[SwiftWrite2xP2, SwiftVLDMPerm2],
 997         (instregex "VST2q(8|16|32)$", "VST2q(8|16|32)Pseudo$")>;
 998   def : InstRW<[SwiftWrite2xP2, SwiftVLDMPerm2],
 999         (instregex "VST2q(8|16|32)wb", "VST2q(8|16|32)PseudoWB")>;
1000   // Three element structure store.
1001   def : InstRW<[SwiftWrite4xP2, SwiftVLDMPerm2],
1002         (instregex "VST3(d|q)(8|16|32)$", "VST3(d|q)(8|16|32)(oddP|P)seudo$")>;
1003   def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2, SwiftVLDMPerm2],
1004         (instregex "VST3(d|q)(8|16|32)_UPD",
1005                    "VST3(d|q)(8|16|32)(oddP|P)seudo_UPD$")>;
1006   // Four element structure store.
1007   def : InstRW<[SwiftWrite4xP2, SwiftVLDMPerm2],
1008         (instregex "VST4(d|q)(8|16|32)$", "VST4(d|q)(8|16|32)(oddP|P)seudo$")>;
1009   def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2, SwiftVLDMPerm4],
1010         (instregex "VST4(d|q)(8|16|32)_UPD",
1011                    "VST4(d|q)(8|16|32)(oddP|P)seudo_UPD$")>;
1012   // Single/all lane store.
1013   // One element structure.
1014   def : InstRW<[SwiftWrite1xP2, SwiftVLDMPerm1],
1015         (instregex "VST1LNd(8|16|32)$", "VST1LNq(8|16|32)Pseudo$")>;
1016   def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2, SwiftVLDMPerm1],
1017         (instregex "VST1LNd(8|16|32)_UPD", "VST1LNq(8|16|32)Pseudo_UPD")>;
1018   // Two element structure.
1019   def : InstRW<[SwiftWrite1xP2, SwiftVLDMPerm2],
1020         (instregex "VST2LN(d|q)(8|16|32)$", "VST2LN(d|q)(8|16|32)Pseudo$")>;
1021   def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2, SwiftVLDMPerm2],
1022         (instregex "VST2LN(d|q)(8|16|32)_UPD",
1023                    "VST2LN(d|q)(8|16|32)Pseudo_UPD")>;
1024   // Three element structure.
1025   def : InstRW<[SwiftWrite4xP2, SwiftVLDMPerm2],
1026         (instregex "VST3LN(d|q)(8|16|32)$", "VST3LN(d|q)(8|16|32)Pseudo$")>;
1027   def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2, SwiftVLDMPerm2],
1028         (instregex "VST3LN(d|q)(8|16|32)_UPD",
1029                    "VST3LN(d|q)(8|16|32)Pseudo_UPD")>;
1030   // Four element structure.
1031   def : InstRW<[SwiftWrite2xP2, SwiftVLDMPerm2],
1032         (instregex "VST4LN(d|q)(8|16|32)$", "VST4LN(d|q)(8|16|32)Pseudo$")>;
1033   def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite2xP2, SwiftVLDMPerm2],
1034         (instregex "VST4LN(d|q)(8|16|32)_UPD",
1035                    "VST4LN(d|q)(8|16|32)Pseudo_UPD")>;
1036
1037   // 4.2.44 VFP, Divide and Square Root
1038   def SwiftDiv17 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
1039     let NumMicroOps = 1;
1040     let Latency = 17;
1041     let ResourceCycles = [1, 15];
1042   }
1043   def SwiftDiv32 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
1044     let NumMicroOps = 1;
1045     let Latency = 32;
1046     let ResourceCycles = [1, 30];
1047   }
1048   def : InstRW<[SwiftDiv17], (instregex "VDIVS", "VSQRTS")>;
1049   def : InstRW<[SwiftDiv32], (instregex "VDIVD", "VSQRTD")>;
1050
1051   // ===---------------------------------------------------------------------===//
1052   // Floating-point. Map target defined SchedReadWrite to processor specific ones
1053   //
1054   def : SchedAlias<WriteFPCVT, SwiftWriteP1FourCycle>;
1055   def : SchedAlias<WriteFPMOV, SwiftWriteP2ThreeCycle>;
1056
1057   def : SchedAlias<WriteFPALU32, SwiftWriteP0FourCycle>;
1058   def : SchedAlias<WriteFPALU64, SwiftWriteP0SixCycle>;
1059
1060   def : SchedAlias<WriteFPMUL32, SwiftWriteP1FourCycle>;
1061   def : SchedAlias<WriteFPMUL64, SwiftWriteP1SixCycle>;
1062
1063   def : SchedAlias<WriteFPMAC32, SwiftWriteP1FourCycle>;
1064   def : SchedAlias<WriteFPMAC64, SwiftWriteP1FourCycle>;
1065
1066   def : SchedAlias<WriteFPDIV32, SwiftDiv17>;
1067   def : SchedAlias<WriteFPSQRT32, SwiftDiv17>;
1068
1069   def : SchedAlias<WriteFPDIV64, SwiftDiv32>;
1070   def : SchedAlias<WriteFPSQRT64, SwiftDiv32>;
1071
1072   def : ReadAdvance<ReadFPMUL, 0>;
1073   def : ReadAdvance<ReadFPMAC, 0>;
1074
1075   // Overriden via InstRW for this processor.
1076   def : WriteRes<WriteVLD1, []>;
1077   def : WriteRes<WriteVLD2, []>;
1078   def : WriteRes<WriteVLD3, []>;
1079   def : WriteRes<WriteVLD4, []>;
1080   def : WriteRes<WriteVST1, []>;
1081   def : WriteRes<WriteVST2, []>;
1082   def : WriteRes<WriteVST3, []>;
1083   def : WriteRes<WriteVST4, []>;
1084
1085   // Not specified.
1086   def : InstRW<[SwiftWriteP01OneCycle2x], (instregex "ABS")>;
1087   // Preload.
1088   def : WriteRes<WritePreLd, [SwiftUnitP2]> { let Latency = 0;
1089     let ResourceCycles = [0];
1090   }
1091
1092 }