1 //===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
10 #define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
12 #include "llvm/Support/DataTypes.h"
22 class MCObjectTargetWriter
;
24 class MCSubtargetInfo
;
25 class MCTargetOptions
;
29 class raw_pwrite_stream
;
33 // How many bytes are in the ABI-defined, caller-allocated part of
35 const int64_t CallFrameSize
= 160;
37 // The offset of the DWARF CFA from the incoming stack pointer.
38 const int64_t CFAOffsetFromInitialSP
= CallFrameSize
;
40 // Maps of asm register numbers to LLVM register numbers, with 0 indicating
41 // an invalid register. In principle we could use 32-bit and 64-bit register
42 // classes directly, provided that we relegated the GPR allocation order
43 // in SystemZRegisterInfo.td to an AltOrder and left the default order
44 // as %r0-%r15. It seems better to provide the same interface for
45 // all classes though.
46 extern const unsigned GR32Regs
[16];
47 extern const unsigned GRH32Regs
[16];
48 extern const unsigned GR64Regs
[16];
49 extern const unsigned GR128Regs
[16];
50 extern const unsigned FP32Regs
[16];
51 extern const unsigned FP64Regs
[16];
52 extern const unsigned FP128Regs
[16];
53 extern const unsigned VR32Regs
[32];
54 extern const unsigned VR64Regs
[32];
55 extern const unsigned VR128Regs
[32];
56 extern const unsigned AR32Regs
[16];
57 extern const unsigned CR64Regs
[16];
59 // Return the 0-based number of the first architectural register that
60 // contains the given LLVM register. E.g. R1D -> 1.
61 unsigned getFirstReg(unsigned Reg
);
63 // Return the given register as a GR64.
64 inline unsigned getRegAsGR64(unsigned Reg
) {
65 return GR64Regs
[getFirstReg(Reg
)];
68 // Return the given register as a low GR32.
69 inline unsigned getRegAsGR32(unsigned Reg
) {
70 return GR32Regs
[getFirstReg(Reg
)];
73 // Return the given register as a high GR32.
74 inline unsigned getRegAsGRH32(unsigned Reg
) {
75 return GRH32Regs
[getFirstReg(Reg
)];
78 // Return the given register as a VR128.
79 inline unsigned getRegAsVR128(unsigned Reg
) {
80 return VR128Regs
[getFirstReg(Reg
)];
82 } // end namespace SystemZMC
84 MCCodeEmitter
*createSystemZMCCodeEmitter(const MCInstrInfo
&MCII
,
85 const MCRegisterInfo
&MRI
,
88 MCAsmBackend
*createSystemZMCAsmBackend(const Target
&T
,
89 const MCSubtargetInfo
&STI
,
90 const MCRegisterInfo
&MRI
,
91 const MCTargetOptions
&Options
);
93 std::unique_ptr
<MCObjectTargetWriter
> createSystemZObjectWriter(uint8_t OSABI
);
94 } // end namespace llvm
96 // Defines symbolic names for SystemZ registers.
97 // This defines a mapping from register name to register number.
98 #define GET_REGINFO_ENUM
99 #include "SystemZGenRegisterInfo.inc"
101 // Defines symbolic names for the SystemZ instructions.
102 #define GET_INSTRINFO_ENUM
103 #include "SystemZGenInstrInfo.inc"
105 #define GET_SUBTARGETINFO_ENUM
106 #include "SystemZGenSubtargetInfo.inc"