include/llvm/IR/InlineAsm.h

   1 //===- llvm/InlineAsm.h - Class to represent inline asm strings -*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This class represents the inline asm strings, which are Value*'s that are
  10 // used as the callee operand of call instructions.  InlineAsm's are uniqued
  11 // like constants, and created via InlineAsm::get(...).
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef LLVM_IR_INLINEASM_H
  16 #define LLVM_IR_INLINEASM_H
  17
  18 #include "llvm/ADT/StringRef.h"
  19 #include "llvm/IR/Value.h"
  20 #include <cassert>
  21 #include <string>
  22 #include <vector>
  23
  24 namespace llvm {
  25
  26 class FunctionType;
  27 class PointerType;
  28 template <class ConstantClass> class ConstantUniqueMap;
  29
  30 class InlineAsm final : public Value {
  31 public:
  32   enum AsmDialect {
  33     AD_ATT,
  34     AD_Intel
  35   };
  36
  37 private:
  38   friend struct InlineAsmKeyType;
  39   friend class ConstantUniqueMap<InlineAsm>;
  40
  41   std::string AsmString, Constraints;
  42   FunctionType *FTy;
  43   bool HasSideEffects;
  44   bool IsAlignStack;
  45   AsmDialect Dialect;
  46
  47   InlineAsm(FunctionType *Ty, const std::string &AsmString,
  48             const std::string &Constraints, bool hasSideEffects,
  49             bool isAlignStack, AsmDialect asmDialect);
  50
  51   /// When the ConstantUniqueMap merges two types and makes two InlineAsms
  52   /// identical, it destroys one of them with this method.
  53   void destroyConstant();
  54
  55 public:
  56   InlineAsm(const InlineAsm &) = delete;
  57   InlineAsm &operator=(const InlineAsm &) = delete;
  58
  59   /// InlineAsm::get - Return the specified uniqued inline asm string.
  60   ///
  61   static InlineAsm *get(FunctionType *Ty, StringRef AsmString,
  62                         StringRef Constraints, bool hasSideEffects,
  63                         bool isAlignStack = false,
  64                         AsmDialect asmDialect = AD_ATT);
  65
  66   bool hasSideEffects() const { return HasSideEffects; }
  67   bool isAlignStack() const { return IsAlignStack; }
  68   AsmDialect getDialect() const { return Dialect; }
  69
  70   /// getType - InlineAsm's are always pointers.
  71   ///
  72   PointerType *getType() const {
  73     return reinterpret_cast<PointerType*>(Value::getType());
  74   }
  75
  76   /// getFunctionType - InlineAsm's are always pointers to functions.
  77   ///
  78   FunctionType *getFunctionType() const;
  79
  80   const std::string &getAsmString() const { return AsmString; }
  81   const std::string &getConstraintString() const { return Constraints; }
  82
  83   /// Verify - This static method can be used by the parser to check to see if
  84   /// the specified constraint string is legal for the type.  This returns true
  85   /// if legal, false if not.
  86   ///
  87   static bool Verify(FunctionType *Ty, StringRef Constraints);
  88
  89   // Constraint String Parsing
  90   enum ConstraintPrefix {
  91     isInput,            // 'x'
  92     isOutput,           // '=x'
  93     isClobber           // '~x'
  94   };
  95
  96   using ConstraintCodeVector = std::vector<std::string>;
  97
  98   struct SubConstraintInfo {
  99     /// MatchingInput - If this is not -1, this is an output constraint where an
 100     /// input constraint is required to match it (e.g. "0").  The value is the
 101     /// constraint number that matches this one (for example, if this is
 102     /// constraint #0 and constraint #4 has the value "0", this will be 4).
 103     int MatchingInput = -1;
 104
 105     /// Code - The constraint code, either the register name (in braces) or the
 106     /// constraint letter/number.
 107     ConstraintCodeVector Codes;
 108
 109     /// Default constructor.
 110     SubConstraintInfo() = default;
 111   };
 112
 113   using SubConstraintInfoVector = std::vector<SubConstraintInfo>;
 114   struct ConstraintInfo;
 115   using ConstraintInfoVector = std::vector<ConstraintInfo>;
 116
 117   struct ConstraintInfo {
 118     /// Type - The basic type of the constraint: input/output/clobber
 119     ///
 120     ConstraintPrefix Type = isInput;
 121
 122     /// isEarlyClobber - "&": output operand writes result before inputs are all
 123     /// read.  This is only ever set for an output operand.
 124     bool isEarlyClobber = false;
 125
 126     /// MatchingInput - If this is not -1, this is an output constraint where an
 127     /// input constraint is required to match it (e.g. "0").  The value is the
 128     /// constraint number that matches this one (for example, if this is
 129     /// constraint #0 and constraint #4 has the value "0", this will be 4).
 130     int MatchingInput = -1;
 131
 132     /// hasMatchingInput - Return true if this is an output constraint that has
 133     /// a matching input constraint.
 134     bool hasMatchingInput() const { return MatchingInput != -1; }
 135
 136     /// isCommutative - This is set to true for a constraint that is commutative
 137     /// with the next operand.
 138     bool isCommutative = false;
 139
 140     /// isIndirect - True if this operand is an indirect operand.  This means
 141     /// that the address of the source or destination is present in the call
 142     /// instruction, instead of it being returned or passed in explicitly.  This
 143     /// is represented with a '*' in the asm string.
 144     bool isIndirect = false;
 145
 146     /// Code - The constraint code, either the register name (in braces) or the
 147     /// constraint letter/number.
 148     ConstraintCodeVector Codes;
 149
 150     /// isMultipleAlternative - '|': has multiple-alternative constraints.
 151     bool isMultipleAlternative = false;
 152
 153     /// multipleAlternatives - If there are multiple alternative constraints,
 154     /// this array will contain them.  Otherwise it will be empty.
 155     SubConstraintInfoVector multipleAlternatives;
 156
 157     /// The currently selected alternative constraint index.
 158     unsigned currentAlternativeIndex = 0;
 159
 160     /// Default constructor.
 161     ConstraintInfo() = default;
 162
 163     /// Parse - Analyze the specified string (e.g. "=*&{eax}") and fill in the
 164     /// fields in this structure.  If the constraint string is not understood,
 165     /// return true, otherwise return false.
 166     bool Parse(StringRef Str, ConstraintInfoVector &ConstraintsSoFar);
 167
 168     /// selectAlternative - Point this constraint to the alternative constraint
 169     /// indicated by the index.
 170     void selectAlternative(unsigned index);
 171   };
 172
 173   /// ParseConstraints - Split up the constraint string into the specific
 174   /// constraints and their prefixes.  If this returns an empty vector, and if
 175   /// the constraint string itself isn't empty, there was an error parsing.
 176   static ConstraintInfoVector ParseConstraints(StringRef ConstraintString);
 177
 178   /// ParseConstraints - Parse the constraints of this inlineasm object,
 179   /// returning them the same way that ParseConstraints(str) does.
 180   ConstraintInfoVector ParseConstraints() const {
 181     return ParseConstraints(Constraints);
 182   }
 183
 184   // Methods for support type inquiry through isa, cast, and dyn_cast:
 185   static bool classof(const Value *V) {
 186     return V->getValueID() == Value::InlineAsmVal;
 187   }
 188
 189   // These are helper methods for dealing with flags in the INLINEASM SDNode
 190   // in the backend.
 191   //
 192   // The encoding of the flag word is currently:
 193   //   Bits 2-0 - A Kind_* value indicating the kind of the operand.
 194   //   Bits 15-3 - The number of SDNode operands associated with this inline
 195   //               assembly operand.
 196   //   If bit 31 is set:
 197   //     Bit 30-16 - The operand number that this operand must match.
 198   //                 When bits 2-0 are Kind_Mem, the Constraint_* value must be
 199   //                 obtained from the flags for this operand number.
 200   //   Else if bits 2-0 are Kind_Mem:
 201   //     Bit 30-16 - A Constraint_* value indicating the original constraint
 202   //                 code.
 203   //   Else:
 204   //     Bit 30-16 - The register class ID to use for the operand.
 205
 206   enum : uint32_t {
 207     // Fixed operands on an INLINEASM SDNode.
 208     Op_InputChain = 0,
 209     Op_AsmString = 1,
 210     Op_MDNode = 2,
 211     Op_ExtraInfo = 3,    // HasSideEffects, IsAlignStack, AsmDialect.
 212     Op_FirstOperand = 4,
 213
 214     // Fixed operands on an INLINEASM MachineInstr.
 215     MIOp_AsmString = 0,
 216     MIOp_ExtraInfo = 1,    // HasSideEffects, IsAlignStack, AsmDialect.
 217     MIOp_FirstOperand = 2,
 218
 219     // Interpretation of the MIOp_ExtraInfo bit field.
 220     Extra_HasSideEffects = 1,
 221     Extra_IsAlignStack = 2,
 222     Extra_AsmDialect = 4,
 223     Extra_MayLoad = 8,
 224     Extra_MayStore = 16,
 225     Extra_IsConvergent = 32,
 226
 227     // Inline asm operands map to multiple SDNode / MachineInstr operands.
 228     // The first operand is an immediate describing the asm operand, the low
 229     // bits is the kind:
 230     Kind_RegUse = 1,             // Input register, "r".
 231     Kind_RegDef = 2,             // Output register, "=r".
 232     Kind_RegDefEarlyClobber = 3, // Early-clobber output register, "=&r".
 233     Kind_Clobber = 4,            // Clobbered register, "~r".
 234     Kind_Imm = 5,                // Immediate.
 235     Kind_Mem = 6,                // Memory operand, "m".
 236
 237     // Memory constraint codes.
 238     // These could be tablegenerated but there's little need to do that since
 239     // there's plenty of space in the encoding to support the union of all
 240     // constraint codes for all targets.
 241     Constraint_Unknown = 0,
 242     Constraint_es,
 243     Constraint_i,
 244     Constraint_m,
 245     Constraint_o,
 246     Constraint_v,
 247     Constraint_A,
 248     Constraint_Q,
 249     Constraint_R,
 250     Constraint_S,
 251     Constraint_T,
 252     Constraint_Um,
 253     Constraint_Un,
 254     Constraint_Uq,
 255     Constraint_Us,
 256     Constraint_Ut,
 257     Constraint_Uv,
 258     Constraint_Uy,
 259     Constraint_X,
 260     Constraint_Z,
 261     Constraint_ZC,
 262     Constraint_Zy,
 263     Constraints_Max = Constraint_Zy,
 264     Constraints_ShiftAmount = 16,
 265
 266     Flag_MatchingOperand = 0x80000000
 267   };
 268
 269   static unsigned getFlagWord(unsigned Kind, unsigned NumOps) {
 270     assert(((NumOps << 3) & ~0xffff) == 0 && "Too many inline asm operands!");
 271     assert(Kind >= Kind_RegUse && Kind <= Kind_Mem && "Invalid Kind");
 272     return Kind | (NumOps << 3);
 273   }
 274
 275   static bool isRegDefKind(unsigned Flag){ return getKind(Flag) == Kind_RegDef;}
 276   static bool isImmKind(unsigned Flag) { return getKind(Flag) == Kind_Imm; }
 277   static bool isMemKind(unsigned Flag) { return getKind(Flag) == Kind_Mem; }
 278   static bool isRegDefEarlyClobberKind(unsigned Flag) {
 279     return getKind(Flag) == Kind_RegDefEarlyClobber;
 280   }
 281   static bool isClobberKind(unsigned Flag) {
 282     return getKind(Flag) == Kind_Clobber;
 283   }
 284
 285   /// getFlagWordForMatchingOp - Augment an existing flag word returned by
 286   /// getFlagWord with information indicating that this input operand is tied
 287   /// to a previous output operand.
 288   static unsigned getFlagWordForMatchingOp(unsigned InputFlag,
 289                                            unsigned MatchedOperandNo) {
 290     assert(MatchedOperandNo <= 0x7fff && "Too big matched operand");
 291     assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
 292     return InputFlag | Flag_MatchingOperand | (MatchedOperandNo << 16);
 293   }
 294
 295   /// getFlagWordForRegClass - Augment an existing flag word returned by
 296   /// getFlagWord with the required register class for the following register
 297   /// operands.
 298   /// A tied use operand cannot have a register class, use the register class
 299   /// from the def operand instead.
 300   static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC) {
 301     // Store RC + 1, reserve the value 0 to mean 'no register class'.
 302     ++RC;
 303     assert(!isImmKind(InputFlag) && "Immediates cannot have a register class");
 304     assert(!isMemKind(InputFlag) && "Memory operand cannot have a register class");
 305     assert(RC <= 0x7fff && "Too large register class ID");
 306     assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
 307     return InputFlag | (RC << 16);
 308   }
 309
 310   /// Augment an existing flag word returned by getFlagWord with the constraint
 311   /// code for a memory constraint.
 312   static unsigned getFlagWordForMem(unsigned InputFlag, unsigned Constraint) {
 313     assert(isMemKind(InputFlag) && "InputFlag is not a memory constraint!");
 314     assert(Constraint <= 0x7fff && "Too large a memory constraint ID");
 315     assert(Constraint <= Constraints_Max && "Unknown constraint ID");
 316     assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
 317     return InputFlag | (Constraint << Constraints_ShiftAmount);
 318   }
 319
 320   static unsigned convertMemFlagWordToMatchingFlagWord(unsigned InputFlag) {
 321     assert(isMemKind(InputFlag));
 322     return InputFlag & ~(0x7fff << Constraints_ShiftAmount);
 323   }
 324
 325   static unsigned getKind(unsigned Flags) {
 326     return Flags & 7;
 327   }
 328
 329   static unsigned getMemoryConstraintID(unsigned Flag) {
 330     assert(isMemKind(Flag));
 331     return (Flag >> Constraints_ShiftAmount) & 0x7fff;
 332   }
 333
 334   /// getNumOperandRegisters - Extract the number of registers field from the
 335   /// inline asm operand flag.
 336   static unsigned getNumOperandRegisters(unsigned Flag) {
 337     return (Flag & 0xffff) >> 3;
 338   }
 339
 340   /// isUseOperandTiedToDef - Return true if the flag of the inline asm
 341   /// operand indicates it is an use operand that's matched to a def operand.
 342   static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx) {
 343     if ((Flag & Flag_MatchingOperand) == 0)
 344       return false;
 345     Idx = (Flag & ~Flag_MatchingOperand) >> 16;
 346     return true;
 347   }
 348
 349   /// hasRegClassConstraint - Returns true if the flag contains a register
 350   /// class constraint.  Sets RC to the register class ID.
 351   static bool hasRegClassConstraint(unsigned Flag, unsigned &RC) {
 352     if (Flag & Flag_MatchingOperand)
 353       return false;
 354     unsigned High = Flag >> 16;
 355     // getFlagWordForRegClass() uses 0 to mean no register class, and otherwise
 356     // stores RC + 1.
 357     if (!High)
 358       return false;
 359     RC = High - 1;
 360     return true;
 361   }
 362 };
 363
 364 } // end namespace llvm
 365
 366 #endif // LLVM_IR_INLINEASM_H