lib/Target/Hexagon/HexagonIntrinsicsV5.td

   1 //===- HexagonIntrinsicsV5.td - V5 Instruction intrinsics --*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 def : T_PR_pat <M2_vrcmpys_s1,     int_hexagon_M2_vrcmpys_s1>;
  10 def : T_PPR_pat<M2_vrcmpys_acc_s1, int_hexagon_M2_vrcmpys_acc_s1>;
  11 def : T_PR_pat <M2_vrcmpys_s1rp,   int_hexagon_M2_vrcmpys_s1rp>;
  12
  13 // Vector reduce add unsigned halfwords
  14 def : T_PP_pat<M2_vradduh, int_hexagon_M2_vradduh>;
  15
  16 def: T_RP_pat<A2_addsp,   int_hexagon_A2_addsp>;
  17 def: T_PP_pat<A2_addpsat, int_hexagon_A2_addpsat>;
  18 def: T_PP_pat<A2_minp,    int_hexagon_A2_minp>;
  19 def: T_PP_pat<A2_minup,   int_hexagon_A2_minup>;
  20 def: T_PP_pat<A2_maxp,    int_hexagon_A2_maxp>;
  21 def: T_PP_pat<A2_maxup,   int_hexagon_A2_maxup>;
  22
  23 // Vector reduce multiply word by signed half (32x16)
  24 //Rdd=vrmpyweh(Rss,Rtt)[:<<1]
  25 def : T_PP_pat <M4_vrmpyeh_s0, int_hexagon_M4_vrmpyeh_s0>;
  26 def : T_PP_pat <M4_vrmpyeh_s1, int_hexagon_M4_vrmpyeh_s1>;
  27
  28 //Rdd=vrmpywoh(Rss,Rtt)[:<<1]
  29 def : T_PP_pat <M4_vrmpyoh_s0, int_hexagon_M4_vrmpyoh_s0>;
  30 def : T_PP_pat <M4_vrmpyoh_s1, int_hexagon_M4_vrmpyoh_s1>;
  31
  32 //Rdd+=vrmpyweh(Rss,Rtt)[:<<1]
  33 def : T_PPP_pat <M4_vrmpyeh_acc_s0, int_hexagon_M4_vrmpyeh_acc_s0>;
  34 def : T_PPP_pat <M4_vrmpyeh_acc_s1, int_hexagon_M4_vrmpyeh_acc_s1>;
  35
  36 //Rdd=vrmpywoh(Rss,Rtt)[:<<1]
  37 def : T_PPP_pat <M4_vrmpyoh_acc_s0, int_hexagon_M4_vrmpyoh_acc_s0>;
  38 def : T_PPP_pat <M4_vrmpyoh_acc_s1, int_hexagon_M4_vrmpyoh_acc_s1>;
  39
  40 // Vector multiply halfwords, signed by unsigned
  41 // Rdd=vmpyhsu(Rs,Rt)[:<<1]:sat
  42 def : T_RR_pat <M2_vmpy2su_s0, int_hexagon_M2_vmpy2su_s0>;
  43 def : T_RR_pat <M2_vmpy2su_s1, int_hexagon_M2_vmpy2su_s1>;
  44
  45 // Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
  46 def : T_PRR_pat <M2_vmac2su_s0, int_hexagon_M2_vmac2su_s0>;
  47 def : T_PRR_pat <M2_vmac2su_s1, int_hexagon_M2_vmac2su_s1>;
  48
  49 // Vector polynomial multiply halfwords
  50 // Rdd=vpmpyh(Rs,Rt)
  51 def : T_RR_pat <M4_vpmpyh, int_hexagon_M4_vpmpyh>;
  52 // Rxx[^]=vpmpyh(Rs,Rt)
  53 def : T_PRR_pat <M4_vpmpyh_acc, int_hexagon_M4_vpmpyh_acc>;
  54
  55 // Polynomial multiply words
  56 // Rdd=pmpyw(Rs,Rt)
  57 def : T_RR_pat <M4_pmpyw, int_hexagon_M4_pmpyw>;
  58 // Rxx^=pmpyw(Rs,Rt)
  59 def : T_PRR_pat <M4_pmpyw_acc, int_hexagon_M4_pmpyw_acc>;
  60
  61 //Rxx^=asr(Rss,Rt)
  62 def : T_PPR_pat <S2_asr_r_p_xor, int_hexagon_S2_asr_r_p_xor>;
  63 //Rxx^=asl(Rss,Rt)
  64 def : T_PPR_pat <S2_asl_r_p_xor, int_hexagon_S2_asl_r_p_xor>;
  65 //Rxx^=lsr(Rss,Rt)
  66 def : T_PPR_pat <S2_lsr_r_p_xor, int_hexagon_S2_lsr_r_p_xor>;
  67 //Rxx^=lsl(Rss,Rt)
  68 def : T_PPR_pat <S2_lsl_r_p_xor, int_hexagon_S2_lsl_r_p_xor>;
  69
  70 // Multiply and use upper result
  71 def : T_RR_pat <M2_mpysu_up, int_hexagon_M2_mpysu_up>;
  72 def : T_RR_pat <M2_mpy_up_s1, int_hexagon_M2_mpy_up_s1>;
  73 def : T_RR_pat <M2_hmmpyh_s1, int_hexagon_M2_hmmpyh_s1>;
  74 def : T_RR_pat <M2_hmmpyl_s1, int_hexagon_M2_hmmpyl_s1>;
  75 def : T_RR_pat <M2_mpy_up_s1_sat, int_hexagon_M2_mpy_up_s1_sat>;
  76
  77 def : T_PP_pat <A2_vaddub, int_hexagon_A2_vaddb_map>;
  78 def : T_PP_pat <A2_vsubub, int_hexagon_A2_vsubb_map>;
  79
  80 // Vector reduce add unsigned halfwords
  81 def : T_PP_pat <M2_vraddh, int_hexagon_M2_vraddh>;
  82
  83 def: T_P_pat<S2_brevp, int_hexagon_S2_brevp>;
  84 def: T_P_pat<S2_ct0p,  int_hexagon_S2_ct0p>;
  85 def: T_P_pat<S2_ct1p,  int_hexagon_S2_ct1p>;
  86
  87 def: T_Q_RR_pat<C4_nbitsset,  int_hexagon_C4_nbitsset>;
  88 def: T_Q_RR_pat<C4_nbitsclr,  int_hexagon_C4_nbitsclr>;
  89 def: T_Q_RI_pat<C4_nbitsclri, int_hexagon_C4_nbitsclri>;
  90
  91 def : T_Q_PI_pat<A4_vcmpbeqi,     int_hexagon_A4_vcmpbeqi>;
  92 def : T_Q_PI_pat<A4_vcmpbgti,     int_hexagon_A4_vcmpbgti>;
  93 def : T_Q_PI_pat<A4_vcmpbgtui,    int_hexagon_A4_vcmpbgtui>;
  94 def : T_Q_PI_pat<A4_vcmpheqi,     int_hexagon_A4_vcmpheqi>;
  95 def : T_Q_PI_pat<A4_vcmphgti,     int_hexagon_A4_vcmphgti>;
  96 def : T_Q_PI_pat<A4_vcmphgtui,    int_hexagon_A4_vcmphgtui>;
  97 def : T_Q_PI_pat<A4_vcmpweqi,     int_hexagon_A4_vcmpweqi>;
  98 def : T_Q_PI_pat<A4_vcmpwgti,     int_hexagon_A4_vcmpwgti>;
  99 def : T_Q_PI_pat<A4_vcmpwgtui,    int_hexagon_A4_vcmpwgtui>;
 100 def : T_Q_PP_pat<A4_vcmpbeq_any,  int_hexagon_A4_vcmpbeq_any>;
 101
 102 def : T_Q_RR_pat<A4_cmpbeq,   int_hexagon_A4_cmpbeq>;
 103 def : T_Q_RR_pat<A4_cmpbgt,   int_hexagon_A4_cmpbgt>;
 104 def : T_Q_RR_pat<A4_cmpbgtu,  int_hexagon_A4_cmpbgtu>;
 105 def : T_Q_RR_pat<A4_cmpheq,   int_hexagon_A4_cmpheq>;
 106 def : T_Q_RR_pat<A4_cmphgt,   int_hexagon_A4_cmphgt>;
 107 def : T_Q_RR_pat<A4_cmphgtu,  int_hexagon_A4_cmphgtu>;
 108
 109 def : T_Q_RI_pat<A4_cmpbeqi,  int_hexagon_A4_cmpbeqi>;
 110 def : T_Q_RI_pat<A4_cmpbgti,  int_hexagon_A4_cmpbgti>;
 111 def : T_Q_RI_pat<A4_cmpbgtui, int_hexagon_A4_cmpbgtui>;
 112
 113 def : T_Q_RI_pat<A4_cmpheqi,  int_hexagon_A4_cmpheqi>;
 114 def : T_Q_RI_pat<A4_cmphgti,  int_hexagon_A4_cmphgti>;
 115 def : T_Q_RI_pat<A4_cmphgtui, int_hexagon_A4_cmphgtui>;
 116
 117 def : T_Q_RP_pat<A4_boundscheck, int_hexagon_A4_boundscheck>;
 118 def : T_Q_PR_pat<A4_tlbmatch,    int_hexagon_A4_tlbmatch>;
 119
 120 def : T_RRR_pat <M4_mpyrr_addr,    int_hexagon_M4_mpyrr_addr>;
 121 def : T_IRR_pat <M4_mpyrr_addi,    int_hexagon_M4_mpyrr_addi>;
 122 def : T_IRI_pat <M4_mpyri_addi,    int_hexagon_M4_mpyri_addi>;
 123 def : T_RIR_pat <M4_mpyri_addr_u2, int_hexagon_M4_mpyri_addr_u2>;
 124 def : T_RRI_pat <M4_mpyri_addr,    int_hexagon_M4_mpyri_addr>;
 125 def : T_RRR_pat <M4_mac_up_s1_sat, int_hexagon_M4_mac_up_s1_sat>;
 126 def : T_RRR_pat <M4_nac_up_s1_sat, int_hexagon_M4_nac_up_s1_sat>;
 127
 128 // Complex multiply 32x16
 129 def : T_PR_pat <M4_cmpyi_wh, int_hexagon_M4_cmpyi_wh>;
 130 def : T_PR_pat <M4_cmpyr_wh, int_hexagon_M4_cmpyr_wh>;
 131
 132 def : T_PR_pat <M4_cmpyi_whc, int_hexagon_M4_cmpyi_whc>;
 133 def : T_PR_pat <M4_cmpyr_whc, int_hexagon_M4_cmpyr_whc>;
 134
 135 def : T_PP_pat<A4_andnp, int_hexagon_A4_andnp>;
 136 def : T_PP_pat<A4_ornp,  int_hexagon_A4_ornp>;
 137
 138 // Complex add/sub halfwords/words
 139 def : T_PP_pat <S4_vxaddsubw, int_hexagon_S4_vxaddsubw>;
 140 def : T_PP_pat <S4_vxsubaddw, int_hexagon_S4_vxsubaddw>;
 141 def : T_PP_pat <S4_vxaddsubh, int_hexagon_S4_vxaddsubh>;
 142 def : T_PP_pat <S4_vxsubaddh, int_hexagon_S4_vxsubaddh>;
 143
 144 def : T_PP_pat <S4_vxaddsubhr, int_hexagon_S4_vxaddsubhr>;
 145 def : T_PP_pat <S4_vxsubaddhr, int_hexagon_S4_vxsubaddhr>;
 146
 147 // Extract bitfield
 148 def : T_PP_pat  <S4_extractp_rp, int_hexagon_S4_extractp_rp>;
 149 def : T_RP_pat  <S4_extract_rp, int_hexagon_S4_extract_rp>;
 150 def : T_PII_pat <S4_extractp, int_hexagon_S4_extractp>;
 151 def : T_RII_pat <S4_extract, int_hexagon_S4_extract>;
 152
 153 // Vector conditional negate
 154 // Rdd=vcnegh(Rss,Rt)
 155 def : T_PR_pat <S2_vcnegh, int_hexagon_S2_vcnegh>;
 156
 157 // Shift an immediate left by register amount
 158 def : T_IR_pat<S4_lsli, int_hexagon_S4_lsli>;
 159
 160 // Vector reduce maximum halfwords
 161 def : T_PPR_pat <A4_vrmaxh, int_hexagon_A4_vrmaxh>;
 162 def : T_PPR_pat <A4_vrmaxuh, int_hexagon_A4_vrmaxuh>;
 163
 164 // Vector reduce maximum words
 165 def : T_PPR_pat <A4_vrmaxw, int_hexagon_A4_vrmaxw>;
 166 def : T_PPR_pat <A4_vrmaxuw, int_hexagon_A4_vrmaxuw>;
 167
 168 // Vector reduce minimum halfwords
 169 def : T_PPR_pat <A4_vrminh, int_hexagon_A4_vrminh>;
 170 def : T_PPR_pat <A4_vrminuh, int_hexagon_A4_vrminuh>;
 171
 172 // Vector reduce minimum words
 173 def : T_PPR_pat <A4_vrminw, int_hexagon_A4_vrminw>;
 174 def : T_PPR_pat <A4_vrminuw, int_hexagon_A4_vrminuw>;
 175
 176 // Rotate and reduce bytes
 177 def : Pat <(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2,
 178                                      u2_0ImmPred:$src3),
 179            (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred:$src3)>;
 180
 181 // Rotate and reduce bytes with accumulation
 182 // Rxx+=vrcrotate(Rss,Rt,#u2)
 183 def : Pat <(int_hexagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2,
 184                                          IntRegs:$src3, u2_0ImmPred:$src4),
 185            (S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2,
 186                              IntRegs:$src3, u2_0ImmPred:$src4)>;
 187
 188 // Vector conditional negate
 189 def : T_PPR_pat<S2_vrcnegh, int_hexagon_S2_vrcnegh>;
 190
 191 // Logical xor with xor accumulation
 192 def : T_PPP_pat<M4_xor_xacc, int_hexagon_M4_xor_xacc>;
 193
 194 // ALU64 - Vector min/max byte
 195 def : T_PP_pat <A2_vminb, int_hexagon_A2_vminb>;
 196 def : T_PP_pat <A2_vmaxb, int_hexagon_A2_vmaxb>;
 197
 198 // Shift and add/sub/and/or
 199 def : T_IRI_pat <S4_andi_asl_ri, int_hexagon_S4_andi_asl_ri>;
 200 def : T_IRI_pat <S4_ori_asl_ri,  int_hexagon_S4_ori_asl_ri>;
 201 def : T_IRI_pat <S4_addi_asl_ri, int_hexagon_S4_addi_asl_ri>;
 202 def : T_IRI_pat <S4_subi_asl_ri, int_hexagon_S4_subi_asl_ri>;
 203 def : T_IRI_pat <S4_andi_lsr_ri, int_hexagon_S4_andi_lsr_ri>;
 204 def : T_IRI_pat <S4_ori_lsr_ri,  int_hexagon_S4_ori_lsr_ri>;
 205 def : T_IRI_pat <S4_addi_lsr_ri, int_hexagon_S4_addi_lsr_ri>;
 206 def : T_IRI_pat <S4_subi_lsr_ri, int_hexagon_S4_subi_lsr_ri>;
 207
 208 // Split bitfield
 209 def : T_RI_pat <A4_bitspliti, int_hexagon_A4_bitspliti>;
 210 def : T_RR_pat <A4_bitsplit,  int_hexagon_A4_bitsplit>;
 211
 212 def: T_RR_pat<S4_parity,      int_hexagon_S4_parity>;
 213
 214 def: T_Q_RI_pat<S4_ntstbit_i, int_hexagon_S4_ntstbit_i>;
 215 def: T_Q_RR_pat<S4_ntstbit_r, int_hexagon_S4_ntstbit_r>;
 216
 217 def: T_RI_pat<S4_clbaddi,     int_hexagon_S4_clbaddi>;
 218 def: T_PI_pat<S4_clbpaddi,    int_hexagon_S4_clbpaddi>;
 219 def: T_P_pat <S4_clbpnorm,    int_hexagon_S4_clbpnorm>;
 220
 221 //*******************************************************************
 222 //            ALU32/ALU
 223 //*******************************************************************
 224
 225 // ALU32 / ALU / Logical Operations.
 226 def: T_RR_pat<A4_andn, int_hexagon_A4_andn>;
 227 def: T_RR_pat<A4_orn,  int_hexagon_A4_orn>;
 228
 229 //*******************************************************************
 230 //            ALU32/PERM
 231 //*******************************************************************
 232
 233 // Combine Words Into Doublewords.
 234 def: T_RI_pat<A4_combineri, int_hexagon_A4_combineri, s32_0ImmPred>;
 235 def: T_IR_pat<A4_combineir, int_hexagon_A4_combineir, s32_0ImmPred>;
 236
 237 //*******************************************************************
 238 //           ALU32/PRED
 239 //*******************************************************************
 240
 241 // Compare
 242 def : T_Q_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi, s32_0ImmPred>;
 243 def : T_Q_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei, s32_0ImmPred>;
 244 def : T_Q_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui, u32_0ImmPred>;
 245
 246 // Compare To General Register.
 247 def: T_Q_RR_pat<C4_cmpneq,  int_hexagon_C4_cmpneq>;
 248 def: T_Q_RR_pat<C4_cmplte,  int_hexagon_C4_cmplte>;
 249 def: T_Q_RR_pat<C4_cmplteu, int_hexagon_C4_cmplteu>;
 250
 251 def: T_RR_pat<A4_rcmpeq,  int_hexagon_A4_rcmpeq>;
 252 def: T_RR_pat<A4_rcmpneq, int_hexagon_A4_rcmpneq>;
 253
 254 def: T_RI_pat<A4_rcmpeqi,  int_hexagon_A4_rcmpeqi>;
 255 def: T_RI_pat<A4_rcmpneqi, int_hexagon_A4_rcmpneqi>;
 256
 257 //*******************************************************************
 258 //           CR
 259 //*******************************************************************
 260
 261 // CR / Logical Operations On Predicates.
 262 def: T_Q_QQQ_pat<C4_and_and,  int_hexagon_C4_and_and>;
 263 def: T_Q_QQQ_pat<C4_and_andn, int_hexagon_C4_and_andn>;
 264 def: T_Q_QQQ_pat<C4_and_or,   int_hexagon_C4_and_or>;
 265 def: T_Q_QQQ_pat<C4_and_orn,  int_hexagon_C4_and_orn>;
 266 def: T_Q_QQQ_pat<C4_or_and,   int_hexagon_C4_or_and>;
 267 def: T_Q_QQQ_pat<C4_or_andn,  int_hexagon_C4_or_andn>;
 268 def: T_Q_QQQ_pat<C4_or_or,    int_hexagon_C4_or_or>;
 269 def: T_Q_QQQ_pat<C4_or_orn,   int_hexagon_C4_or_orn>;
 270
 271 //*******************************************************************
 272 //           XTYPE/ALU
 273 //*******************************************************************
 274
 275 // Add And Accumulate.
 276
 277 def : T_RRI_pat <S4_addaddi, int_hexagon_S4_addaddi>;
 278 def : T_RIR_pat <S4_subaddi, int_hexagon_S4_subaddi>;
 279
 280
 281 // XTYPE / ALU / Logical-logical Words.
 282 def : T_RRR_pat <M4_or_xor,   int_hexagon_M4_or_xor>;
 283 def : T_RRR_pat <M4_and_xor,  int_hexagon_M4_and_xor>;
 284 def : T_RRR_pat <M4_or_and,   int_hexagon_M4_or_and>;
 285 def : T_RRR_pat <M4_and_and,  int_hexagon_M4_and_and>;
 286 def : T_RRR_pat <M4_xor_and,  int_hexagon_M4_xor_and>;
 287 def : T_RRR_pat <M4_or_or,    int_hexagon_M4_or_or>;
 288 def : T_RRR_pat <M4_and_or,   int_hexagon_M4_and_or>;
 289 def : T_RRR_pat <M4_xor_or,   int_hexagon_M4_xor_or>;
 290 def : T_RRR_pat <M4_or_andn,  int_hexagon_M4_or_andn>;
 291 def : T_RRR_pat <M4_and_andn, int_hexagon_M4_and_andn>;
 292 def : T_RRR_pat <M4_xor_andn, int_hexagon_M4_xor_andn>;
 293
 294 def : T_RRI_pat <S4_or_andi, int_hexagon_S4_or_andi>;
 295 def : T_RRI_pat <S4_or_andix,  int_hexagon_S4_or_andix>;
 296 def : T_RRI_pat <S4_or_ori, int_hexagon_S4_or_ori>;
 297
 298 // Modulo wrap.
 299 def : T_RR_pat <A4_modwrapu, int_hexagon_A4_modwrapu>;
 300
 301 // Arithmetic/Convergent round
 302 // Rd=[cround|round](Rs,Rt)[:sat]
 303 // Rd=[cround|round](Rs,#u5)[:sat]
 304 def : T_RI_pat <A4_cround_ri, int_hexagon_A4_cround_ri>;
 305 def : T_RR_pat <A4_cround_rr, int_hexagon_A4_cround_rr>;
 306
 307 def : T_RI_pat <A4_round_ri, int_hexagon_A4_round_ri>;
 308 def : T_RR_pat <A4_round_rr, int_hexagon_A4_round_rr>;
 309
 310 def : T_RI_pat <A4_round_ri_sat, int_hexagon_A4_round_ri_sat>;
 311 def : T_RR_pat <A4_round_rr_sat, int_hexagon_A4_round_rr_sat>;
 312
 313 def : T_P_pat <A2_roundsat, int_hexagon_A2_roundsat>;
 314
 315 //Rdd[+]=vrmpybsu(Rss,Rtt)
 316 //Rdd[+]=vrmpybuu(Rss,Rtt)
 317 def : T_PP_pat  <M5_vrmpybsu, int_hexagon_M5_vrmpybsu>;
 318 def : T_PP_pat  <M5_vrmpybuu, int_hexagon_M5_vrmpybuu>;
 319
 320 def : T_PP_pat <M5_vdmpybsu, int_hexagon_M5_vdmpybsu>;
 321
 322 def : T_PPP_pat <M5_vrmacbsu, int_hexagon_M5_vrmacbsu>;
 323 def : T_PPP_pat <M5_vrmacbuu, int_hexagon_M5_vrmacbuu>;
 324 //Rxx+=vdmpybsu(Rss,Rtt):sat
 325 def : T_PPP_pat <M5_vdmacbsu, int_hexagon_M5_vdmacbsu>;
 326
 327 // Vector multiply bytes
 328 // Rdd=vmpyb[s]u(Rs,Rt)
 329 def : T_RR_pat <M5_vmpybsu, int_hexagon_M5_vmpybsu>;
 330 def : T_RR_pat <M5_vmpybuu, int_hexagon_M5_vmpybuu>;
 331
 332 // Rxx+=vmpyb[s]u(Rs,Rt)
 333 def : T_PRR_pat <M5_vmacbsu, int_hexagon_M5_vmacbsu>;
 334 def : T_PRR_pat <M5_vmacbuu, int_hexagon_M5_vmacbuu>;
 335
 336 // Rd=vaddhub(Rss,Rtt):sat
 337 def : T_PP_pat <A5_vaddhubs, int_hexagon_A5_vaddhubs>;
 338
 339 def : T_FF_pat<F2_sfadd, int_hexagon_F2_sfadd>;
 340 def : T_FF_pat<F2_sfsub, int_hexagon_F2_sfsub>;
 341 def : T_FF_pat<F2_sfmpy, int_hexagon_F2_sfmpy>;
 342 def : T_FF_pat<F2_sfmax, int_hexagon_F2_sfmax>;
 343 def : T_FF_pat<F2_sfmin, int_hexagon_F2_sfmin>;
 344
 345 def : T_FF_pat<F2_sffixupn, int_hexagon_F2_sffixupn>;
 346 def : T_FF_pat<F2_sffixupd, int_hexagon_F2_sffixupd>;
 347 def : T_F_pat <F2_sffixupr, int_hexagon_F2_sffixupr>;
 348
 349 def : T_Q_QQ_pat<C4_fastcorner9,     int_hexagon_C4_fastcorner9>;
 350 def : T_Q_QQ_pat<C4_fastcorner9_not, int_hexagon_C4_fastcorner9_not>;
 351
 352 def : T_P_pat <S5_popcountp, int_hexagon_S5_popcountp>;
 353 def : T_PI_pat <S5_asrhub_sat, int_hexagon_S5_asrhub_sat>;
 354
 355 def : T_PI_pat <S2_asr_i_p_rnd, int_hexagon_S2_asr_i_p_rnd>;
 356 def : T_PI_pat <S2_asr_i_p_rnd_goodsyntax,
 357                 int_hexagon_S2_asr_i_p_rnd_goodsyntax>;
 358
 359 def : T_PI_pat <S5_asrhub_rnd_sat_goodsyntax,
 360                 int_hexagon_S5_asrhub_rnd_sat_goodsyntax>;
 361
 362 def : T_PI_pat <S5_vasrhrnd_goodsyntax, int_hexagon_S5_vasrhrnd_goodsyntax>;
 363
 364 def : T_FFF_pat <F2_sffma, int_hexagon_F2_sffma>;
 365 def : T_FFF_pat <F2_sffms, int_hexagon_F2_sffms>;
 366 def : T_FFF_pat <F2_sffma_lib, int_hexagon_F2_sffma_lib>;
 367 def : T_FFF_pat <F2_sffms_lib, int_hexagon_F2_sffms_lib>;
 368 def : T_FFFQ_pat <F2_sffma_sc, int_hexagon_F2_sffma_sc>;
 369
 370 // Compare floating-point value
 371 def : T_Q_FF_pat <F2_sfcmpge, int_hexagon_F2_sfcmpge>;
 372 def : T_Q_FF_pat <F2_sfcmpuo, int_hexagon_F2_sfcmpuo>;
 373 def : T_Q_FF_pat <F2_sfcmpeq, int_hexagon_F2_sfcmpeq>;
 374 def : T_Q_FF_pat <F2_sfcmpgt, int_hexagon_F2_sfcmpgt>;
 375
 376 def : T_Q_DD_pat <F2_dfcmpeq, int_hexagon_F2_dfcmpeq>;
 377 def : T_Q_DD_pat <F2_dfcmpgt, int_hexagon_F2_dfcmpgt>;
 378 def : T_Q_DD_pat <F2_dfcmpge, int_hexagon_F2_dfcmpge>;
 379 def : T_Q_DD_pat <F2_dfcmpuo, int_hexagon_F2_dfcmpuo>;
 380
 381 // Create floating-point value
 382 def : T_I_pat <F2_sfimm_p, int_hexagon_F2_sfimm_p>;
 383 def : T_I_pat <F2_sfimm_n, int_hexagon_F2_sfimm_n>;
 384 def : T_I_pat <F2_dfimm_p, int_hexagon_F2_dfimm_p>;
 385 def : T_I_pat <F2_dfimm_n, int_hexagon_F2_dfimm_n>;
 386
 387 def : T_Q_DI_pat <F2_dfclass, int_hexagon_F2_dfclass>;
 388 def : T_Q_FI_pat <F2_sfclass, int_hexagon_F2_sfclass>;
 389 def : T_F_pat <F2_conv_sf2df, int_hexagon_F2_conv_sf2df>;
 390 def : T_D_pat <F2_conv_df2sf, int_hexagon_F2_conv_df2sf>;
 391 def : T_R_pat <F2_conv_uw2sf, int_hexagon_F2_conv_uw2sf>;
 392 def : T_R_pat <F2_conv_uw2df, int_hexagon_F2_conv_uw2df>;
 393 def : T_R_pat <F2_conv_w2sf,  int_hexagon_F2_conv_w2sf>;
 394 def : T_R_pat <F2_conv_w2df,  int_hexagon_F2_conv_w2df>;
 395 def : T_P_pat <F2_conv_ud2sf, int_hexagon_F2_conv_ud2sf>;
 396 def : T_P_pat <F2_conv_ud2df, int_hexagon_F2_conv_ud2df>;
 397 def : T_P_pat <F2_conv_d2sf,  int_hexagon_F2_conv_d2sf>;
 398 def : T_P_pat <F2_conv_d2df,  int_hexagon_F2_conv_d2df>;
 399 def : T_F_pat <F2_conv_sf2uw, int_hexagon_F2_conv_sf2uw>;
 400 def : T_F_pat <F2_conv_sf2w,  int_hexagon_F2_conv_sf2w>;
 401 def : T_F_pat <F2_conv_sf2ud, int_hexagon_F2_conv_sf2ud>;
 402 def : T_F_pat <F2_conv_sf2d,  int_hexagon_F2_conv_sf2d>;
 403 def : T_D_pat <F2_conv_df2uw, int_hexagon_F2_conv_df2uw>;
 404 def : T_D_pat <F2_conv_df2w,  int_hexagon_F2_conv_df2w>;
 405 def : T_D_pat <F2_conv_df2ud, int_hexagon_F2_conv_df2ud>;
 406 def : T_D_pat <F2_conv_df2d,  int_hexagon_F2_conv_df2d>;
 407 def : T_F_pat <F2_conv_sf2uw_chop, int_hexagon_F2_conv_sf2uw_chop>;
 408 def : T_F_pat <F2_conv_sf2w_chop,  int_hexagon_F2_conv_sf2w_chop>;
 409 def : T_F_pat <F2_conv_sf2ud_chop, int_hexagon_F2_conv_sf2ud_chop>;
 410 def : T_F_pat <F2_conv_sf2d_chop,  int_hexagon_F2_conv_sf2d_chop>;
 411 def : T_D_pat <F2_conv_df2uw_chop, int_hexagon_F2_conv_df2uw_chop>;
 412 def : T_D_pat <F2_conv_df2w_chop,  int_hexagon_F2_conv_df2w_chop>;
 413 def : T_D_pat <F2_conv_df2ud_chop, int_hexagon_F2_conv_df2ud_chop>;
 414 def : T_D_pat <F2_conv_df2d_chop,  int_hexagon_F2_conv_df2d_chop>;