lib/Target/SystemZ/SystemZInstrInfo.h

   1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains the SystemZ implementation of the TargetInstrInfo class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
  14 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
  15
  16 #include "SystemZ.h"
  17 #include "SystemZRegisterInfo.h"
  18 #include "llvm/ADT/ArrayRef.h"
  19 #include "llvm/CodeGen/MachineBasicBlock.h"
  20 #include "llvm/CodeGen/MachineFunction.h"
  21 #include "llvm/CodeGen/MachineInstrBuilder.h"
  22 #include "llvm/CodeGen/TargetInstrInfo.h"
  23 #include <cstdint>
  24
  25 #define GET_INSTRINFO_HEADER
  26 #include "SystemZGenInstrInfo.inc"
  27
  28 namespace llvm {
  29
  30 class SystemZSubtarget;
  31
  32 namespace SystemZII {
  33
  34 enum {
  35   // See comments in SystemZInstrFormats.td.
  36   SimpleBDXLoad          = (1 << 0),
  37   SimpleBDXStore         = (1 << 1),
  38   Has20BitOffset         = (1 << 2),
  39   HasIndex               = (1 << 3),
  40   Is128Bit               = (1 << 4),
  41   AccessSizeMask         = (31 << 5),
  42   AccessSizeShift        = 5,
  43   CCValuesMask           = (15 << 10),
  44   CCValuesShift          = 10,
  45   CompareZeroCCMaskMask  = (15 << 14),
  46   CompareZeroCCMaskShift = 14,
  47   CCMaskFirst            = (1 << 18),
  48   CCMaskLast             = (1 << 19),
  49   IsLogical              = (1 << 20)
  50 };
  51
  52 static inline unsigned getAccessSize(unsigned int Flags) {
  53   return (Flags & AccessSizeMask) >> AccessSizeShift;
  54 }
  55
  56 static inline unsigned getCCValues(unsigned int Flags) {
  57   return (Flags & CCValuesMask) >> CCValuesShift;
  58 }
  59
  60 static inline unsigned getCompareZeroCCMask(unsigned int Flags) {
  61   return (Flags & CompareZeroCCMaskMask) >> CompareZeroCCMaskShift;
  62 }
  63
  64 // SystemZ MachineOperand target flags.
  65 enum {
  66   // Masks out the bits for the access model.
  67   MO_SYMBOL_MODIFIER = (3 << 0),
  68
  69   // @GOT (aka @GOTENT)
  70   MO_GOT = (1 << 0),
  71
  72   // @INDNTPOFF
  73   MO_INDNTPOFF = (2 << 0)
  74 };
  75
  76 // Classifies a branch.
  77 enum BranchType {
  78   // An instruction that branches on the current value of CC.
  79   BranchNormal,
  80
  81   // An instruction that peforms a 32-bit signed comparison and branches
  82   // on the result.
  83   BranchC,
  84
  85   // An instruction that peforms a 32-bit unsigned comparison and branches
  86   // on the result.
  87   BranchCL,
  88
  89   // An instruction that peforms a 64-bit signed comparison and branches
  90   // on the result.
  91   BranchCG,
  92
  93   // An instruction that peforms a 64-bit unsigned comparison and branches
  94   // on the result.
  95   BranchCLG,
  96
  97   // An instruction that decrements a 32-bit register and branches if
  98   // the result is nonzero.
  99   BranchCT,
 100
 101   // An instruction that decrements a 64-bit register and branches if
 102   // the result is nonzero.
 103   BranchCTG,
 104
 105   // An instruction representing an asm goto statement.
 106   AsmGoto
 107 };
 108
 109 // Information about a branch instruction.
 110 class Branch {
 111   // The target of the branch. In case of INLINEASM_BR, this is nullptr.
 112   const MachineOperand *Target;
 113
 114 public:
 115   // The type of the branch.
 116   BranchType Type;
 117
 118   // CCMASK_<N> is set if CC might be equal to N.
 119   unsigned CCValid;
 120
 121   // CCMASK_<N> is set if the branch should be taken when CC == N.
 122   unsigned CCMask;
 123
 124   Branch(BranchType type, unsigned ccValid, unsigned ccMask,
 125          const MachineOperand *target)
 126     : Target(target), Type(type), CCValid(ccValid), CCMask(ccMask) {}
 127
 128   bool isIndirect() { return Target != nullptr && Target->isReg(); }
 129   bool hasMBBTarget() { return Target != nullptr && Target->isMBB(); }
 130   MachineBasicBlock *getMBBTarget() {
 131     return hasMBBTarget() ? Target->getMBB() : nullptr;
 132   }
 133 };
 134
 135 // Kinds of fused compares in compare-and-* instructions.  Together with type
 136 // of the converted compare, this identifies the compare-and-*
 137 // instruction.
 138 enum FusedCompareType {
 139   // Relative branch - CRJ etc.
 140   CompareAndBranch,
 141
 142   // Indirect branch, used for return - CRBReturn etc.
 143   CompareAndReturn,
 144
 145   // Indirect branch, used for sibcall - CRBCall etc.
 146   CompareAndSibcall,
 147
 148   // Trap
 149   CompareAndTrap
 150 };
 151
 152 } // end namespace SystemZII
 153
 154 namespace SystemZ {
 155 int getTwoOperandOpcode(uint16_t Opcode);
 156 int getTargetMemOpcode(uint16_t Opcode);
 157 }
 158
 159 class SystemZInstrInfo : public SystemZGenInstrInfo {
 160   const SystemZRegisterInfo RI;
 161   SystemZSubtarget &STI;
 162
 163   void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
 164   void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
 165   void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode,
 166                       bool ConvertHigh) const;
 167   void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
 168                        unsigned LowOpcodeK, unsigned HighOpcode) const;
 169   void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
 170                        unsigned HighOpcode) const;
 171   void expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
 172                        unsigned HighOpcode) const;
 173   void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
 174                         unsigned Size) const;
 175   void expandLoadStackGuard(MachineInstr *MI) const;
 176
 177   MachineInstrBuilder
 178   emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
 179                 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
 180                 unsigned LowLowOpcode, unsigned Size, bool KillSrc,
 181                 bool UndefSrc) const;
 182
 183   virtual void anchor();
 184
 185 protected:
 186   /// Commutes the operands in the given instruction by changing the operands
 187   /// order and/or changing the instruction's opcode and/or the immediate value
 188   /// operand.
 189   ///
 190   /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
 191   /// to be commuted.
 192   ///
 193   /// Do not call this method for a non-commutable instruction or
 194   /// non-commutable operands.
 195   /// Even though the instruction is commutable, the method may still
 196   /// fail to commute the operands, null pointer is returned in such cases.
 197   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
 198                                        unsigned CommuteOpIdx1,
 199                                        unsigned CommuteOpIdx2) const override;
 200
 201 public:
 202   explicit SystemZInstrInfo(SystemZSubtarget &STI);
 203
 204   // Override TargetInstrInfo.
 205   unsigned isLoadFromStackSlot(const MachineInstr &MI,
 206                                int &FrameIndex) const override;
 207   unsigned isStoreToStackSlot(const MachineInstr &MI,
 208                               int &FrameIndex) const override;
 209   bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
 210                        int &SrcFrameIndex) const override;
 211   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
 212                      MachineBasicBlock *&FBB,
 213                      SmallVectorImpl<MachineOperand> &Cond,
 214                      bool AllowModify) const override;
 215   unsigned removeBranch(MachineBasicBlock &MBB,
 216                         int *BytesRemoved = nullptr) const override;
 217   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 218                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
 219                         const DebugLoc &DL,
 220                         int *BytesAdded = nullptr) const override;
 221   bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
 222                       unsigned &SrcReg2, int &Mask, int &Value) const override;
 223   bool canInsertSelect(const MachineBasicBlock&, ArrayRef<MachineOperand> Cond,
 224                        unsigned, unsigned, int&, int&, int&) const override;
 225   void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
 226                     const DebugLoc &DL, unsigned DstReg,
 227                     ArrayRef<MachineOperand> Cond, unsigned TrueReg,
 228                     unsigned FalseReg) const override;
 229   bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
 230                      MachineRegisterInfo *MRI) const override;
 231   bool isPredicable(const MachineInstr &MI) const override;
 232   bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
 233                            unsigned ExtraPredCycles,
 234                            BranchProbability Probability) const override;
 235   bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
 236                            unsigned NumCyclesT, unsigned ExtraPredCyclesT,
 237                            MachineBasicBlock &FMBB,
 238                            unsigned NumCyclesF, unsigned ExtraPredCyclesF,
 239                            BranchProbability Probability) const override;
 240   bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
 241                             BranchProbability Probability) const override;
 242   bool PredicateInstruction(MachineInstr &MI,
 243                             ArrayRef<MachineOperand> Pred) const override;
 244   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
 245                    const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
 246                    bool KillSrc) const override;
 247   void storeRegToStackSlot(MachineBasicBlock &MBB,
 248                            MachineBasicBlock::iterator MBBI,
 249                            unsigned SrcReg, bool isKill, int FrameIndex,
 250                            const TargetRegisterClass *RC,
 251                            const TargetRegisterInfo *TRI) const override;
 252   void loadRegFromStackSlot(MachineBasicBlock &MBB,
 253                             MachineBasicBlock::iterator MBBI,
 254                             unsigned DestReg, int FrameIdx,
 255                             const TargetRegisterClass *RC,
 256                             const TargetRegisterInfo *TRI) const override;
 257   MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
 258                                       MachineInstr &MI,
 259                                       LiveVariables *LV) const override;
 260   MachineInstr *
 261   foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
 262                         ArrayRef<unsigned> Ops,
 263                         MachineBasicBlock::iterator InsertPt, int FrameIndex,
 264                         LiveIntervals *LIS = nullptr,
 265                         VirtRegMap *VRM = nullptr) const override;
 266   MachineInstr *foldMemoryOperandImpl(
 267       MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
 268       MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
 269       LiveIntervals *LIS = nullptr) const override;
 270   bool expandPostRAPseudo(MachineInstr &MBBI) const override;
 271   bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
 272     override;
 273
 274   // Return the SystemZRegisterInfo, which this class owns.
 275   const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
 276
 277   // Return the size in bytes of MI.
 278   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
 279
 280   // Return true if MI is a conditional or unconditional branch.
 281   // When returning true, set Cond to the mask of condition-code
 282   // values on which the instruction will branch, and set Target
 283   // to the operand that contains the branch target.  This target
 284   // can be a register or a basic block.
 285   SystemZII::Branch getBranchInfo(const MachineInstr &MI) const;
 286
 287   // Get the load and store opcodes for a given register class.
 288   void getLoadStoreOpcodes(const TargetRegisterClass *RC,
 289                            unsigned &LoadOpcode, unsigned &StoreOpcode) const;
 290
 291   // Opcode is the opcode of an instruction that has an address operand,
 292   // and the caller wants to perform that instruction's operation on an
 293   // address that has displacement Offset.  Return the opcode of a suitable
 294   // instruction (which might be Opcode itself) or 0 if no such instruction
 295   // exists.
 296   unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
 297
 298   // If Opcode is a load instruction that has a LOAD AND TEST form,
 299   // return the opcode for the testing form, otherwise return 0.
 300   unsigned getLoadAndTest(unsigned Opcode) const;
 301
 302   // Return true if ROTATE AND ... SELECTED BITS can be used to select bits
 303   // Mask of the R2 operand, given that only the low BitSize bits of Mask are
 304   // significant.  Set Start and End to the I3 and I4 operands if so.
 305   bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
 306                    unsigned &Start, unsigned &End) const;
 307
 308   // If Opcode is a COMPARE opcode for which an associated fused COMPARE AND *
 309   // operation exists, return the opcode for the latter, otherwise return 0.
 310   // MI, if nonnull, is the compare instruction.
 311   unsigned getFusedCompare(unsigned Opcode,
 312                            SystemZII::FusedCompareType Type,
 313                            const MachineInstr *MI = nullptr) const;
 314
 315   // If Opcode is a LOAD opcode for with an associated LOAD AND TRAP
 316   // operation exists, returh the opcode for the latter, otherwise return 0.
 317   unsigned getLoadAndTrap(unsigned Opcode) const;
 318
 319   // Emit code before MBBI in MI to move immediate value Value into
 320   // physical register Reg.
 321   void loadImmediate(MachineBasicBlock &MBB,
 322                      MachineBasicBlock::iterator MBBI,
 323                      unsigned Reg, uint64_t Value) const;
 324
 325   // Sometimes, it is possible for the target to tell, even without
 326   // aliasing information, that two MIs access different memory
 327   // addresses. This function returns true if two MIs access different
 328   // memory addresses and false otherwise.
 329   bool
 330   areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
 331                                   const MachineInstr &MIb) const override;
 332 };
 333
 334 } // end namespace llvm
 335
 336 #endif // LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H