| blob | 2b69c13174f6c8f0223016a47bae064a005fdbd3 |
1 # RUN: llc -run-pass machine-cse -verify-machineinstrs -mtriple aarch64-apple-ios %s -o - | FileCheck %s
2 ---
3 name: irtranslated
4 legalized: false
5 regBankSelected: false
6 selected: false
7 body: |
8 ; CHECK-LABEL: name: irtranslated
9 ; CHECK: %[[ONE:[0-9]+]]:_(s32) = G_CONSTANT i32 1
10 ; CHECK-NEXT: %[[TWO:[0-9]+]]:_(s32) = G_ADD %[[ONE]], %[[ONE]]
11 ; CHECK-NEXT: %[[SUM:[0-9]+]]:_(s32) = G_ADD %[[TWO]], %[[TWO]]
12 ; CHECK-NEXT: $[[RET:[wx][0-9]+]] = COPY %[[SUM]](s32)
13 ; CHECK-NEXT: RET_ReallyLR implicit $[[RET]]
14 bb.0:
15 %0:_(s32) = G_CONSTANT i32 1
16 %1:_(s32) = G_ADD %0, %0
17 %2:_(s32) = G_ADD %0, %0
18 %3:_(s32) = G_ADD %1, %2
19 $w0 = COPY %3(s32)
20 RET_ReallyLR implicit $w0
21 ...
22 ---
23 name: regbankselected
24 legalized: true
25 regBankSelected: true
26 selected: false
27 body: |
28 ; CHECK-LABEL: name: regbankselected
29 ; CHECK: %[[ONE:[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
30 ; CHECK-NEXT: %[[TWO:[0-9]+]]:gpr(s32) = G_ADD %[[ONE]], %[[ONE]]
31 ; CHECK-NEXT: %[[SUM:[0-9]+]]:gpr(s32) = G_ADD %[[TWO]], %[[TWO]]
32 ; CHECK-NEXT: $[[RET:[wx][0-9]+]] = COPY %[[SUM]](s32)
33 ; CHECK-NEXT: RET_ReallyLR implicit $[[RET]]
34 bb.0:
35 %0:gpr(s32) = G_CONSTANT i32 1
36 %1:gpr(s32) = G_ADD %0, %0
37 %2:gpr(s32) = G_ADD %0, %0
38 %3:gpr(s32) = G_ADD %1, %2
39 $w0 = COPY %3(s32)
40 RET_ReallyLR implicit $w0
41 ...
42 ---
43 name: legalized
44 legalized: true
45 regBankSelected: false
46 selected: false
47 body: |
48 ; CHECK-LABEL: name: legalized
49 ; CHECK: %[[ONE:[0-9]+]]:_(s32) = G_CONSTANT i32 1
50 ; CHECK-NEXT: %[[TWO:[0-9]+]]:gpr(s32) = G_ADD %[[ONE]], %[[ONE]]
51 ; CHECK-NEXT: %[[SUM:[0-9]+]]:_(s32) = G_ADD %[[TWO]], %[[TWO]]
52 ; CHECK-NEXT: $[[RET:[wx][0-9]+]] = COPY %[[SUM]](s32)
53 ; CHECK-NEXT: RET_ReallyLR implicit $[[RET]]
54 bb.0:
55 %0:_(s32) = G_CONSTANT i32 1
56 %1:_(s32) = G_ADD %0, %0
57 %2:gpr(s32) = G_ADD %0, %0
58 %3:_(s32) = G_ADD %1, %2
59 $w0 = COPY %3(s32)
60 RET_ReallyLR implicit $w0
61 ...
62 ---
63 name: legalized_sym
64 legalized: true
65 regBankSelected: false
66 selected: false
67 body: |
68 ; CHECK-LABEL: name: legalized_sym
69 ; CHECK: %[[ONE:[0-9]+]]:_(s32) = G_CONSTANT i32 1
70 ; CHECK-NEXT: %[[TWO:[0-9]+]]:gpr(s32) = G_ADD %[[ONE]], %[[ONE]]
71 ; CHECK-NEXT: %[[SUM:[0-9]+]]:_(s32) = G_ADD %[[TWO]], %[[TWO]]
72 ; CHECK-NEXT: $[[RET:[wx][0-9]+]] = COPY %[[SUM]](s32)
73 ; CHECK-NEXT: RET_ReallyLR implicit $[[RET]]
74 bb.0:
75 %0:_(s32) = G_CONSTANT i32 1
76 %1:gpr(s32) = G_ADD %0, %0
77 %2:_(s32) = G_ADD %0, %0
78 %3:_(s32) = G_ADD %1, %2
79 $w0 = COPY %3(s32)
80 RET_ReallyLR implicit $w0
81 ...
82 ---
83 name: int_extensions
84 alignment: 4
85 legalized: false
86 regBankSelected: false
87 selected: false
88 body: |
89 ; CHECK-LABEL: name: int_extensions
90 ; CHECK: %[[ONE:[0-9]+]]:_(s8) = G_CONSTANT i8 1
91 ; CHECK-NEXT: %[[S16:[0-9]+]]:_(s16) = G_SEXT %[[ONE]](s8)
92 ; CHECK-NEXT: %[[S32:[0-9]+]]:_(s32) = G_SEXT %[[ONE]](s8)
93 ; CHECK-NEXT: %[[S16_Z64:[0-9]+]]:_(s64) = G_ZEXT %[[S16]](s16)
94 ; CHECK-NEXT: %[[S32_Z64:[0-9]+]]:_(s64) = G_ZEXT %[[S32]](s32)
95 ; CHECK-NEXT: %[[SUM:[0-9]+]]:_(s64) = G_ADD %[[S16_Z64]], %[[S32_Z64]]
96 ; CHECK-NEXT: $[[RET:[wx][0-9]+]] = COPY %[[SUM]](s64)
97 ; CHECK-NEXT: RET_ReallyLR implicit $[[RET]]
98 bb.0.entry:
99 %0:_(s8) = G_CONSTANT i8 1
100 %1:_(s16) = G_SEXT %0(s8)
101 %2:_(s32) = G_SEXT %0(s8)
102 %3:_(s64) = G_ZEXT %1(s16)
103 %4:_(s64) = G_ZEXT %2(s32)
104 %5:_(s64) = G_ADD %3, %4
105 $x0 = COPY %5(s64)
106 RET_ReallyLR implicit $x0
107 ...
108 ---
109 name: generic
110 legalized: true
111 regBankSelected: false
112 selected: false
113 body: |
114 ; CHECK-LABEL: name: generic
115 ; CHECK: %[[SG:[0-9]+]]:_(s32) = G_ADD %{{[0-9]+}}, %{{[0-9]+}}
116 ; CHECK-NEXT: %{{[0-9]+}}:_(s32) = G_ADD %[[SG]], %[[SG]]
117 bb.0:
118 %0:_(s32) = COPY $w0
119 %1:_(s32) = COPY $w1
120 %2:_(s32) = G_ADD %0, %1
121 %3:_(s32) = COPY %2(s32)
122 %4:_(s32) = G_ADD %3, %3
123 $w0 = COPY %4(s32)
124 RET_ReallyLR implicit $w0
125 ...
126 ---
127 name: generic_to_concrete_copy
128 legalized: true
129 regBankSelected: false
130 selected: false
131 body: |
132 ; CHECK-LABEL: name: generic_to_concrete_copy
133 ; CHECK: %[[S1:[0-9]+]]:gpr32(s32) = G_ADD %{{[0-9]+}}, %{{[0-9]+}}
134 ; CHECK-NEXT: %{{[0-9]+}}:gpr32 = ADDWrr %[[S1]](s32), %[[S1]](s32)
135 bb.0:
136 %0:_(s32) = COPY $w0
137 %1:_(s32) = COPY $w1
138 %2:_(s32) = G_ADD %0, %1
139 %3:gpr32 = COPY %2(s32)
140 %4:gpr32 = ADDWrr %3, %3
141 $w0 = COPY %4
142 RET_ReallyLR implicit $w0
143 ...
144 ---
145 name: concrete_to_generic_copy
146 legalized: true
147 regBankSelected: false
148 selected: false
149 body: |
150 ; CHECK-LABEL: name: concrete_to_generic_copy
151 ; CHECK: %[[S1:[0-9]+]]:gpr32(s32) = ADDWrr %{{[0-9]+}}, %{{[0-9]+}}
152 ; CHECK-NEXT: %{{[0-9]+}}:_(s32) = G_ADD %[[S1]], %[[S1]]
153 bb.0:
154 %0:gpr32 = COPY $w0
155 %1:gpr32 = COPY $w1
156 %2:gpr32 = ADDWrr %0, %1
157 %3:_(s32) = COPY %2
158 %4:_(s32) = G_ADD %3, %3
159 $w0 = COPY %4(s32)
160 RET_ReallyLR implicit $w0
161 ...
162 ---
163 name: concrete
164 legalized: true
165 regBankSelected: false
166 selected: false
167 body: |
168 ; CHECK-LABEL: name: concrete
169 ; CHECK: %[[SC:[0-9]+]]:gpr32 = ADDWrr %{{[0-9]+}}, %{{[0-9]+}}
170 ; CHECK-NEXT: %{{[0-9]+}}:gpr32 = ADDWrr %[[SC]], %[[SC]]
171 bb.0:
172 %0:gpr32 = COPY $w0
173 %1:gpr32 = COPY $w1
174 %2:gpr32 = ADDWrr %0, %1
175 %3:gpr32 = COPY %2
176 %4:gpr32 = ADDWrr %3, %3
177 $w0 = COPY %4
178 RET_ReallyLR implicit $w0
179 ...
180 ---
181 name: variadic_defs_unmerge_vector
182 legalized: true
183 regBankSelected: false
184 selected: false
185 body: |
186 ; CHECK-LABEL: name: variadic_defs_unmerge_vector
187 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
188 ; CHECK-NEXT: [[UV0:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
189 ; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s32) = G_ANYEXT [[UV0]](s16)
190 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
191 ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
192 ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
193 ; CHECK-NEXT: [[ADD0:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT0]], [[ANYEXT1]]
194 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT2]], [[ANYEXT3]]
195 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD0]], [[ADD1]]
196 ; CHECK-NEXT: $w0 = COPY [[ADD2]](s32)
197 ; CHECK-NEXT: RET_ReallyLR implicit $w0
198 bb.0:
199 %0 :_(<4 x s16>) = COPY $d0
200 %1 :_(s16), %2 :_(s16), %3 :_(s16), %4 :_(s16) = G_UNMERGE_VALUES %0(<4 x s16>)
201 %5 :_(s16), %6 :_(s16), %7 :_(s16), %8 :_(s16) = G_UNMERGE_VALUES %0(<4 x s16>)
202 %9 :_(s16), %10:_(s16), %11:_(s16), %12:_(s16) = G_UNMERGE_VALUES %0(<4 x s16>)
203 %13:_(s16), %14:_(s16), %15:_(s16), %16:_(s16) = G_UNMERGE_VALUES %0(<4 x s16>)
204 %17:_(s32) = G_ANYEXT %1 (s16)
205 %18:_(s32) = G_ANYEXT %6 (s16)
206 %19:_(s32) = G_ANYEXT %11(s16)
207 %20:_(s32) = G_ANYEXT %16(s16)
208 %21:_(s32) = G_ADD %17, %18
209 %22:_(s32) = G_ADD %19, %20
210 %23:_(s32) = G_ADD %21, %22
211 $w0 = COPY %23(s32)
212 RET_ReallyLR implicit $w0
213 ...
214 ---
215 name: variadic_defs_unmerge_scalar
216 legalized: true
217 regBankSelected: false
218 selected: false
219 body: |
220 ; CHECK-LABEL: name: variadic_defs_unmerge_scalar
221 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
222 ; CHECK-NEXT: [[UV0:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](s64)
223 ; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s32) = G_ANYEXT [[UV0]](s16)
224 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
225 ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
226 ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
227 ; CHECK-NEXT: [[ADD0:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT0]], [[ANYEXT1]]
228 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT2]], [[ANYEXT3]]
229 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD0]], [[ADD1]]
230 ; CHECK-NEXT: $w0 = COPY [[ADD2]](s32)
231 ; CHECK-NEXT: RET_ReallyLR implicit $w0
232 bb.0:
233 %0 :_(s64) = COPY $d0
234 %1 :_(s16), %2 :_(s16), %3 :_(s16), %4 :_(s16) = G_UNMERGE_VALUES %0(s64)
235 %5 :_(s16), %6 :_(s16), %7 :_(s16), %8 :_(s16) = G_UNMERGE_VALUES %0(s64)
236 %9 :_(s16), %10:_(s16), %11:_(s16), %12:_(s16) = G_UNMERGE_VALUES %0(s64)
237 %13:_(s16), %14:_(s16), %15:_(s16), %16:_(s16) = G_UNMERGE_VALUES %0(s64)
238 %17:_(s32) = G_ANYEXT %1 (s16)
239 %18:_(s32) = G_ANYEXT %6 (s16)
240 %19:_(s32) = G_ANYEXT %11(s16)
241 %20:_(s32) = G_ANYEXT %16(s16)
242 %21:_(s32) = G_ADD %17, %18
243 %22:_(s32) = G_ADD %19, %20
244 %23:_(s32) = G_ADD %21, %22
245 $w0 = COPY %23(s32)
246 RET_ReallyLR implicit $w0
247 ...
248 ---
249 name: variadic_defs_unmerge_scalar_asym
250 legalized: true
251 regBankSelected: false
252 selected: false
253 body: |
254 ; CHECK-LABEL: name: variadic_defs_unmerge_scalar_asym
255 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
256 ; CHECK-NEXT: [[UV0:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](s64)
257 ; CHECK-NEXT: [[UV01:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
258 ; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s32) = G_ANYEXT [[UV0]](s16)
259 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
260 ; CHECK-NEXT: [[ADD0:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT0]], [[ANYEXT1]]
261 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV01]], [[UV23]]
262 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD0]], [[ADD1]]
263 ; CHECK-NEXT: $w0 = COPY [[ADD2]](s32)
264 ; CHECK-NEXT: RET_ReallyLR implicit $w0
265 bb.0:
266 %0 :_(s64) = COPY $d0
267 %1 :_(s16), %2 :_(s16), %3 :_(s16), %4 :_(s16) = G_UNMERGE_VALUES %0(s64)
268 %9 :_(s32), %10:_(s32) = G_UNMERGE_VALUES %0(s64)
269 %5 :_(s16), %6 :_(s16), %7 :_(s16), %8 :_(s16) = G_UNMERGE_VALUES %0(s64)
270 %11:_(s32), %12:_(s32) = G_UNMERGE_VALUES %0(s64)
271 %17:_(s32) = G_ANYEXT %1 (s16)
272 %18:_(s32) = G_ANYEXT %6 (s16)
273 %21:_(s32) = G_ADD %17, %18
274 %22:_(s32) = G_ADD %9, %12
275 %23:_(s32) = G_ADD %21, %22
276 $w0 = COPY %23(s32)
277 RET_ReallyLR implicit $w0
278 ...
279 ---
280 name: variadic_defs_unmerge_vector_constraints_mix
281 legalized: true
282 regBankSelected: false
283 selected: false
284 body: |
285 ; CHECK-LABEL: name: variadic_defs_unmerge_vector_constraints_mix
286 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
287 ; CHECK-NEXT: [[UV0:%[0-9]+]]:gpr(s32), [[UV1:%[0-9]+]]:gpr(s32), [[UV2:%[0-9]+]]:gpr32(s32), [[UV3:%[0-9]+]]:gpr32(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
288 ; CHECK-NEXT: [[ADD0:%[0-9]+]]:_(s32) = G_ADD [[UV0]], [[UV1]]
289 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr32(s32) = ADDWrr [[UV2]](s32), [[UV3]](s32)
290 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD0]], [[ADD1]]
291 ; CHECK-NEXT: $w0 = COPY [[ADD2]](s32)
292 ; CHECK-NEXT: RET_ReallyLR implicit $w0
293 bb.0:
294 %0 :_(<4 x s32>) = COPY $q0
295 %1 :_(s32), %2 : _ (s32), %3 :_(s32), %4 : _ (s32) = G_UNMERGE_VALUES %0(<4 x s32>)
296 %5 :_(s32), %6 :gpr(s32), %7 :_(s32), %8 : _ (s32) = G_UNMERGE_VALUES %0(<4 x s32>)
297 %9 :_(s32), %10: _ (s32), %11:_(s32), %12: _ (s32) = G_UNMERGE_VALUES %0(<4 x s32>)
298 %13:_(s32), %14: _ (s32), %15:_(s32), %16:gpr32(s32) = G_UNMERGE_VALUES %0(<4 x s32>)
299 %21:gpr(s32) = COPY %1(s32)
300 %17:_(s32) = G_ADD %21, %6
301 %18:gpr32 = COPY %11(s32)
302 %19:gpr32(s32) = ADDWrr %18, %16
303 %20:_(s32) = G_ADD %17, %19
304 $w0 = COPY %20(s32)
305 RET_ReallyLR implicit $w0
306 ...