test/MC/AArch64/SVE/ld1w-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Immediate out of lower bound [-8, 7].
   5
   6 ld1w z30.s, p6/z, [x25, #-9, MUL VL]
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
   8 // CHECK-NEXT: ld1w z30.s, p6/z, [x25, #-9, MUL VL]
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 ld1w z29.s, p5/z, [x15, #8, MUL VL]
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
  13 // CHECK-NEXT: ld1w z29.s, p5/z, [x15, #8, MUL VL]
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 ld1w z28.d, p2/z, [x28, #-9, MUL VL]
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
  18 // CHECK-NEXT: ld1w z28.d, p2/z, [x28, #-9, MUL VL]
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 ld1w z27.d, p1/z, [x26, #8, MUL VL]
  22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
  23 // CHECK-NEXT: ld1w z27.d, p1/z, [x26, #8, MUL VL]
  24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  25
  26
  27 // --------------------------------------------------------------------------//
  28 // restricted predicate has range [0, 7].
  29
  30 ld1w z12.s, p8/z, [x13, #1, MUL VL]
  31 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  32 // CHECK-NEXT: ld1w z12.s, p8/z, [x13, #1, MUL VL]
  33 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  34
  35 ld1w z4.d, p8/z, [x11, #1, MUL VL]
  36 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  37 // CHECK-NEXT: ld1w z4.d, p8/z, [x11, #1, MUL VL]
  38 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  39
  40
  41 // --------------------------------------------------------------------------//
  42 // Invalid vector list.
  43
  44 ld1w { }, p0/z, [x1, #1, MUL VL]
  45 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
  46 // CHECK-NEXT: ld1w { }, p0/z, [x1, #1, MUL VL]
  47 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  48
  49 ld1w { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
  50 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  51 // CHECK-NEXT: ld1w { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
  52 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  53
  54 ld1w { v0.2d }, p0/z, [x1, #1, MUL VL]
  55 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  56 // CHECK-NEXT: ld1w { v0.2d }, p0/z, [x1, #1, MUL VL]
  57 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  58
  59
  60 // --------------------------------------------------------------------------//
  61 // Invalid scalar + scalar addressing modes
  62
  63 ld1w z0.s, p0/z, [x0, x0]
  64 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
  65 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, x0]
  66 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  67
  68 ld1w z0.s, p0/z, [x0, xzr]
  69 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
  70 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, xzr]
  71 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  72
  73 ld1w z0.s, p0/z, [x0, x0, lsl #3]
  74 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
  75 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, x0, lsl #3]
  76 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  77
  78 ld1w z0.s, p0/z, [x0, w0]
  79 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
  80 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, w0]
  81 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  82
  83 ld1w z0.s, p0/z, [x0, w0, uxtw]
  84 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
  85 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, w0, uxtw]
  86 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  87
  88
  89 // --------------------------------------------------------------------------//
  90 // Invalid scalar + vector addressing modes
  91
  92 ld1w z0.d, p0/z, [x0, z0.h]
  93 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  94 // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.h]
  95 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  96
  97 ld1w z0.d, p0/z, [x0, z0.s]
  98 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
  99 // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.s]
 100 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 101
 102 ld1w z0.s, p0/z, [x0, z0.s]
 103 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 104 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, z0.s]
 105 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 106
 107 ld1w z0.s, p0/z, [x0, z0.s, uxtw #3]
 108 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
 109 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, z0.s, uxtw #3]
 110 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 111
 112 ld1w z0.s, p0/z, [x0, z0.s, lsl #2]
 113 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
 114 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, z0.s, lsl #2]
 115 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 116
 117 ld1w z0.d, p0/z, [x0, z0.d, lsl #3]
 118 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
 119 // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.d, lsl #3]
 120 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 121
 122 ld1w z0.d, p0/z, [x0, z0.d, sxtw #3]
 123 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
 124 // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.d, sxtw #3]
 125 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 126
 127
 128 // --------------------------------------------------------------------------//
 129 // Invalid vector + immediate addressing modes
 130
 131 ld1w z0.s, p0/z, [z0.s, #-4]
 132 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
 133 // CHECK-NEXT: ld1w z0.s, p0/z, [z0.s, #-4]
 134 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 135
 136 ld1w z0.s, p0/z, [z0.s, #-1]
 137 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
 138 // CHECK-NEXT: ld1w z0.s, p0/z, [z0.s, #-1]
 139 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 140
 141 ld1w z0.s, p0/z, [z0.s, #125]
 142 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
 143 // CHECK-NEXT: ld1w z0.s, p0/z, [z0.s, #125]
 144 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 145
 146 ld1w z0.s, p0/z, [z0.s, #128]
 147 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
 148 // CHECK-NEXT: ld1w z0.s, p0/z, [z0.s, #128]
 149 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 150
 151 ld1w z0.s, p0/z, [z0.s, #3]
 152 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
 153 // CHECK-NEXT: ld1w z0.s, p0/z, [z0.s, #3]
 154 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 155
 156 ld1w z0.d, p0/z, [z0.d, #-4]
 157 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
 158 // CHECK-NEXT: ld1w z0.d, p0/z, [z0.d, #-4]
 159 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 160
 161 ld1w z0.d, p0/z, [z0.d, #-1]
 162 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
 163 // CHECK-NEXT: ld1w z0.d, p0/z, [z0.d, #-1]
 164 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 165
 166 ld1w z0.d, p0/z, [z0.d, #125]
 167 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
 168 // CHECK-NEXT: ld1w z0.d, p0/z, [z0.d, #125]
 169 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 170
 171 ld1w z0.d, p0/z, [z0.d, #128]
 172 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
 173 // CHECK-NEXT: ld1w z0.d, p0/z, [z0.d, #128]
 174 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 175
 176 ld1w z0.d, p0/z, [z0.d, #3]
 177 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
 178 // CHECK-NEXT: ld1w z0.d, p0/z, [z0.d, #3]
 179 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 180
 181
 182 // --------------------------------------------------------------------------//
 183 // Negative tests for instructions that are incompatible with movprfx
 184
 185 movprfx z0.d, p0/z, z7.d
 186 ld1w    { z0.d }, p0/z, [z0.d]
 187 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
 188 // CHECK-NEXT: ld1w    { z0.d }, p0/z, [z0.d]
 189 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 190
 191 movprfx z0, z7
 192 ld1w    { z0.d }, p0/z, [z0.d]
 193 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
 194 // CHECK-NEXT: ld1w    { z0.d }, p0/z, [z0.d]
 195 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: