[InstCombine] Signed saturation patterns
[llvm-core.git] / test / MC / Hexagon / vpred_defs.s
blob92c15a3e575809ab266883e4428ef608ff416cb7
1 # RUN: llvm-mc -arch=hexagon -mv65 -filetype=asm -mhvx %s | FileCheck %s
3 # CHECK-NOT: error: register `{{.+}}' modified more than once
5 { Q0 = VCMP.EQ(V0.h,V4.h)
6 Q1 = VCMP.EQ(V1.h,V6.h)
7 IF (Q3) VTMP.h = VGATHER(R0,M0,V3.h).h
8 VMEM(R4++#1) = VTMP.new