[InstCombine] Signed saturation patterns

[llvm-core.git] / test / Transforms / InstCombine / 2007-01-18-VectorInfLoop.ll

; RUN: opt < %s -instcombine -disable-output

define <4 x i32> @test(<4 x i32> %A) {
    %B = xor <4 x i32> %A, < i32 -1, i32 -1, i32 -1, i32 -1 > 
    %C = and <4 x i32> %B, < i32 -1, i32 -1, i32 -1, i32 -1 >
    ret <4 x i32> %C
}