| blob | a53bf6cc028919c47cd92dbe9648d6347e29458a |
1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt < %s -instcombine -S | FileCheck %s
4 define i64 @test_sext_zext(i16 %A) {
5 ; CHECK-LABEL: @test_sext_zext(
6 ; CHECK-NEXT: [[C2:%.*]] = zext i16 %A to i64
7 ; CHECK-NEXT: ret i64 [[C2]]
8 ;
9 %c1 = zext i16 %A to i32
10 %c2 = sext i32 %c1 to i64
11 ret i64 %c2
12 }
14 define <2 x i64> @test2(<2 x i1> %A) {
15 ; CHECK-LABEL: @test2(
16 ; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i1> %A, <i1 true, i1 true>
17 ; CHECK-NEXT: [[ZEXT:%.*]] = zext <2 x i1> [[XOR]] to <2 x i64>
18 ; CHECK-NEXT: ret <2 x i64> [[ZEXT]]
19 ;
20 %xor = xor <2 x i1> %A, <i1 true, i1 true>
21 %zext = zext <2 x i1> %xor to <2 x i64>
22 ret <2 x i64> %zext
23 }
25 define <2 x i64> @test3(<2 x i64> %A) {
26 ; CHECK-LABEL: @test3(
27 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i64> %A, <i64 23, i64 42>
28 ; CHECK-NEXT: ret <2 x i64> [[AND]]
29 ;
30 %trunc = trunc <2 x i64> %A to <2 x i32>
31 %and = and <2 x i32> %trunc, <i32 23, i32 42>
32 %zext = zext <2 x i32> %and to <2 x i64>
33 ret <2 x i64> %zext
34 }
36 define <2 x i64> @test4(<2 x i64> %A) {
37 ; CHECK-LABEL: @test4(
38 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i64> [[A:%.*]], <i64 23, i64 42>
39 ; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i64> [[AND]], <i64 23, i64 42>
40 ; CHECK-NEXT: ret <2 x i64> [[XOR]]
41 ;
42 %trunc = trunc <2 x i64> %A to <2 x i32>
43 %and = and <2 x i32> %trunc, <i32 23, i32 42>
44 %xor = xor <2 x i32> %and, <i32 23, i32 42>
45 %zext = zext <2 x i32> %xor to <2 x i64>
46 ret <2 x i64> %zext
47 }
49 define i64 @fold_xor_zext_sandwich(i1 %a) {
50 ; CHECK-LABEL: @fold_xor_zext_sandwich(
51 ; CHECK-NEXT: [[TMP1:%.*]] = xor i1 %a, true
52 ; CHECK-NEXT: [[ZEXT2:%.*]] = zext i1 [[TMP1]] to i64
53 ; CHECK-NEXT: ret i64 [[ZEXT2]]
54 ;
55 %zext1 = zext i1 %a to i32
56 %xor = xor i32 %zext1, 1
57 %zext2 = zext i32 %xor to i64
58 ret i64 %zext2
59 }
61 define <2 x i64> @fold_xor_zext_sandwich_vec(<2 x i1> %a) {
62 ; CHECK-LABEL: @fold_xor_zext_sandwich_vec(
63 ; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i1> %a, <i1 true, i1 true>
64 ; CHECK-NEXT: [[ZEXT2:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i64>
65 ; CHECK-NEXT: ret <2 x i64> [[ZEXT2]]
66 ;
67 %zext1 = zext <2 x i1> %a to <2 x i32>
68 %xor = xor <2 x i32> %zext1, <i32 1, i32 1>
69 %zext2 = zext <2 x i32> %xor to <2 x i64>
70 ret <2 x i64> %zext2
71 }
73 ; Assert that zexts in and(zext(icmp), zext(icmp)) can be folded.
75 define i8 @fold_and_zext_icmp(i64 %a, i64 %b, i64 %c) {
76 ; CHECK-LABEL: @fold_and_zext_icmp(
77 ; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 %a, %b
78 ; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i64 %a, %c
79 ; CHECK-NEXT: [[TMP3:%.*]] = and i1 [[TMP1]], [[TMP2]]
80 ; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i8
81 ; CHECK-NEXT: ret i8 [[TMP4]]
82 ;
83 %1 = icmp sgt i64 %a, %b
84 %2 = zext i1 %1 to i8
85 %3 = icmp slt i64 %a, %c
86 %4 = zext i1 %3 to i8
87 %5 = and i8 %2, %4
88 ret i8 %5
89 }
91 ; Assert that zexts in or(zext(icmp), zext(icmp)) can be folded.
93 define i8 @fold_or_zext_icmp(i64 %a, i64 %b, i64 %c) {
94 ; CHECK-LABEL: @fold_or_zext_icmp(
95 ; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 %a, %b
96 ; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i64 %a, %c
97 ; CHECK-NEXT: [[TMP3:%.*]] = or i1 [[TMP1]], [[TMP2]]
98 ; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i8
99 ; CHECK-NEXT: ret i8 [[TMP4]]
100 ;
101 %1 = icmp sgt i64 %a, %b
102 %2 = zext i1 %1 to i8
103 %3 = icmp slt i64 %a, %c
104 %4 = zext i1 %3 to i8
105 %5 = or i8 %2, %4
106 ret i8 %5
107 }
109 ; Assert that zexts in xor(zext(icmp), zext(icmp)) can be folded.
111 define i8 @fold_xor_zext_icmp(i64 %a, i64 %b, i64 %c) {
112 ; CHECK-LABEL: @fold_xor_zext_icmp(
113 ; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 %a, %b
114 ; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i64 %a, %c
115 ; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP1]], [[TMP2]]
116 ; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i8
117 ; CHECK-NEXT: ret i8 [[TMP4]]
118 ;
119 %1 = icmp sgt i64 %a, %b
120 %2 = zext i1 %1 to i8
121 %3 = icmp slt i64 %a, %c
122 %4 = zext i1 %3 to i8
123 %5 = xor i8 %2, %4
124 ret i8 %5
125 }
127 ; Assert that zexts in logic(zext(icmp), zext(icmp)) are also folded accross
128 ; nested logical operators.
130 define i8 @fold_nested_logic_zext_icmp(i64 %a, i64 %b, i64 %c, i64 %d) {
131 ; CHECK-LABEL: @fold_nested_logic_zext_icmp(
132 ; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 %a, %b
133 ; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i64 %a, %c
134 ; CHECK-NEXT: [[TMP3:%.*]] = and i1 [[TMP1]], [[TMP2]]
135 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 %a, %d
136 ; CHECK-NEXT: [[TMP5:%.*]] = or i1 [[TMP3]], [[TMP4]]
137 ; CHECK-NEXT: [[TMP6:%.*]] = zext i1 [[TMP5]] to i8
138 ; CHECK-NEXT: ret i8 [[TMP6]]
139 ;
140 %1 = icmp sgt i64 %a, %b
141 %2 = zext i1 %1 to i8
142 %3 = icmp slt i64 %a, %c
143 %4 = zext i1 %3 to i8
144 %5 = and i8 %2, %4
145 %6 = icmp eq i64 %a, %d
146 %7 = zext i1 %6 to i8
147 %8 = or i8 %5, %7
148 ret i8 %8
149 }
151 ; This test is for Integer BitWidth > 64 && BitWidth <= 1024.
153 define i1024 @sext_zext_apint1(i77 %A) {
154 ; CHECK-LABEL: @sext_zext_apint1(
155 ; CHECK-NEXT: [[C2:%.*]] = zext i77 %A to i1024
156 ; CHECK-NEXT: ret i1024 [[C2]]
157 ;
158 %c1 = zext i77 %A to i533
159 %c2 = sext i533 %c1 to i1024
160 ret i1024 %c2
161 }
163 ; This test is for Integer BitWidth <= 64 && BitWidth % 2 != 0.
165 define i47 @sext_zext_apint2(i11 %A) {
166 ; CHECK-LABEL: @sext_zext_apint2(
167 ; CHECK-NEXT: [[C2:%.*]] = zext i11 %A to i47
168 ; CHECK-NEXT: ret i47 [[C2]]
169 ;
170 %c1 = zext i11 %A to i39
171 %c2 = sext i39 %c1 to i47
172 ret i47 %c2
173 }