[InstCombine] Signed saturation patterns
[llvm-core.git] / test / tools / llvm-mca / X86 / BdVer2 / instruction-info-view.s
blobc8c32506a979d69f394cc5989cc94b1fa8fdb346
1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -resource-pressure=false -instruction-info=true < %s | FileCheck %s --check-prefix=ENABLED
3 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -resource-pressure=false -instruction-info=false < %s | FileCheck %s -check-prefix=DISABLED
4 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -resource-pressure=false -instruction-info < %s | FileCheck %s -check-prefix=ENABLED
5 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -resource-pressure=false < %s | FileCheck %s -check-prefix=ENABLED
7 vmulps %xmm0, %xmm1, %xmm2
8 vhaddps %xmm2, %xmm2, %xmm3
9 vhaddps %xmm3, %xmm3, %xmm4
11 # DISABLED-NOT: Instruction Info:
14 # ENABLED: Iterations: 100
15 # ENABLED-NEXT: Instructions: 300
16 # ENABLED-NEXT: Total Cycles: 583
17 # ENABLED-NEXT: Total uOps: 700
20 # ENABLED: Dispatch Width: 4
21 # ENABLED-NEXT: uOps Per Cycle: 1.20
22 # ENABLED-NEXT: IPC: 0.51
23 # ENABLED-NEXT: Block RThroughput: 5.5
25 # ENABLED: Instruction Info:
26 # ENABLED-NEXT: [1]: #uOps
27 # ENABLED-NEXT: [2]: Latency
28 # ENABLED-NEXT: [3]: RThroughput
29 # ENABLED-NEXT: [4]: MayLoad
30 # ENABLED-NEXT: [5]: MayStore
31 # ENABLED-NEXT: [6]: HasSideEffects (U)
33 # ENABLED: [1] [2] [3] [4] [5] [6] Instructions:
34 # ENABLED-NEXT: 1 5 1.00 vmulps %xmm0, %xmm1, %xmm2
35 # ENABLED-NEXT: 3 11 2.50 vhaddps %xmm2, %xmm2, %xmm3
36 # ENABLED-NEXT: 3 11 2.50 vhaddps %xmm3, %xmm3, %xmm4