[InstCombine] Signed saturation patterns
[llvm-core.git] / test / tools / llvm-mca / X86 / Generic / resources-clwb.s
blob099edcda15aed3b81a4ad4bd2f6f6bab5df85391
1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s
4 clwb (%rax)
6 # CHECK: Instruction Info:
7 # CHECK-NEXT: [1]: #uOps
8 # CHECK-NEXT: [2]: Latency
9 # CHECK-NEXT: [3]: RThroughput
10 # CHECK-NEXT: [4]: MayLoad
11 # CHECK-NEXT: [5]: MayStore
12 # CHECK-NEXT: [6]: HasSideEffects (U)
14 # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
15 # CHECK-NEXT: 1 5 0.50 * * U clwb (%rax)
17 # CHECK: Resources:
18 # CHECK-NEXT: [0] - SBDivider
19 # CHECK-NEXT: [1] - SBFPDivider
20 # CHECK-NEXT: [2] - SBPort0
21 # CHECK-NEXT: [3] - SBPort1
22 # CHECK-NEXT: [4] - SBPort4
23 # CHECK-NEXT: [5] - SBPort5
24 # CHECK-NEXT: [6.0] - SBPort23
25 # CHECK-NEXT: [6.1] - SBPort23
27 # CHECK: Resource pressure per iteration:
28 # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1]
29 # CHECK-NEXT: - - - - - - 0.50 0.50
31 # CHECK: Resource pressure by instruction:
32 # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
33 # CHECK-NEXT: - - - - - - 0.50 0.50 clwb (%rax)