[ARM] Adjust how NEON shifts are lowered
[llvm-core.git] / test / tools / llvm-mca / AArch64 / Exynos / direct-branch.s
blobcd31d0b39fba730de5e4c7e1885ea408888f6472
1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2 # RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m1 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M1
3 # RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M3
4 # RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4
6 b main
8 # ALL: Iterations: 100
9 # ALL-NEXT: Instructions: 100
11 # M1-NEXT: Total Cycles: 26
12 # M3-NEXT: Total Cycles: 18
13 # M4-NEXT: Total Cycles: 18
15 # ALL-NEXT: Total uOps: 100
17 # M1: Dispatch Width: 4
18 # M1-NEXT: uOps Per Cycle: 3.85
19 # M1-NEXT: IPC: 3.85
20 # M1-NEXT: Block RThroughput: 0.3
22 # M3: Dispatch Width: 6
23 # M3-NEXT: uOps Per Cycle: 5.56
24 # M3-NEXT: IPC: 5.56
25 # M3-NEXT: Block RThroughput: 0.2
27 # M4: Dispatch Width: 6
28 # M4-NEXT: uOps Per Cycle: 5.56
29 # M4-NEXT: IPC: 5.56
30 # M4-NEXT: Block RThroughput: 0.2
32 # ALL: Instruction Info:
33 # ALL-NEXT: [1]: #uOps
34 # ALL-NEXT: [2]: Latency
35 # ALL-NEXT: [3]: RThroughput
36 # ALL-NEXT: [4]: MayLoad
37 # ALL-NEXT: [5]: MayStore
38 # ALL-NEXT: [6]: HasSideEffects (U)
40 # ALL: [1] [2] [3] [4] [5] [6] Instructions:
42 # M1-NEXT: 1 0 0.25 b main
43 # M3-NEXT: 1 0 0.17 b main
44 # M4-NEXT: 1 0 0.17 b main