[ARM] Adjust how NEON shifts are lowered
[llvm-core.git] / test / tools / llvm-mca / AArch64 / Exynos / scheduler-queue-usage.s
blob7249998a7800dfb94d41cd78a8d6f01538c80d35
1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2 # RUN: llvm-mca -march=aarch64 -mcpu=exynos-m1 -iterations=1 -scheduler-stats -resource-pressure=false -instruction-info=false < %s | FileCheck %s -check-prefixes=ALL,M1
3 # RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -iterations=1 -scheduler-stats -resource-pressure=false -instruction-info=false < %s | FileCheck %s -check-prefixes=ALL,M3
4 # RUN: llvm-mca -march=aarch64 -mcpu=exynos-m4 -iterations=1 -scheduler-stats -resource-pressure=false -instruction-info=false < %s | FileCheck %s -check-prefixes=ALL,M4
6 b main
8 # ALL: Iterations: 1
9 # ALL-NEXT: Instructions: 1
10 # ALL-NEXT: Total Cycles: 2
11 # ALL-NEXT: Total uOps: 1
13 # M1: Dispatch Width: 4
14 # M1-NEXT: uOps Per Cycle: 0.50
15 # M1-NEXT: IPC: 0.50
16 # M1-NEXT: Block RThroughput: 0.3
18 # M3: Dispatch Width: 6
19 # M3-NEXT: uOps Per Cycle: 0.50
20 # M3-NEXT: IPC: 0.50
21 # M3-NEXT: Block RThroughput: 0.2
23 # M4: Dispatch Width: 6
24 # M4-NEXT: uOps Per Cycle: 0.50
25 # M4-NEXT: IPC: 0.50
26 # M4-NEXT: Block RThroughput: 0.2
28 # ALL: Schedulers - number of cycles where we saw N micro opcodes issued:
29 # ALL-NEXT: [# issued], [# cycles]
30 # ALL-NEXT: 0, 1 (50.0%)
31 # ALL-NEXT: 1, 1 (50.0%)
33 # ALL: Scheduler's queue usage:
34 # ALL-NEXT: No scheduler resources used.