[ARM] Fixup the creation of VPT blocks
[llvm-core.git] / test / CodeGen / AArch64 / f16-imm.ll
blob84c27312d1e120e7bc4d8b5d792a0a93447e9ae1
1 ; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ILLEGAL
2 ; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16,+zcz | FileCheck %s --check-prefix=CHECK-ZCZ
3 ; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=-fullfp16 | FileCheck %s --check-prefix=CHECK-NOFP16 --check-prefix=CHECK-ILLEGAL
5 define half @Const0() {
6 entry:
7   ret half 0xH0000
9 ; CHECK-DAG-ILLEGAL-LABEL:  Const0:
10 ; CHECK-DAG-ILLEGAL-NEXT:   fmov  h0, wzr
11 ; CHECK-DAG-ILLEGAL-NEXT:   ret
13 ; CHECK-ZCZ-LABEL:  Const0:
14 ; CHECK-ZCZ:        movi  v0.2d, #0000000000000000
15 ; CHECK-ZCZ-NEXT:   ret
17 define half @Const1() {
18 entry:
19   ret half 0xH3C00
21 ; CHECK-DAG-LABEL: Const1:
22 ; CHECK-DAG-NEXT:   fmov h0, #1.00000000
23 ; CHECK-DAG-NEXT:   ret
25 ; CHECK-NOFP16:        .[[LBL1:LCPI1_[0-9]]]:
26 ; CHECK-NOFP16-NEXT:   .hword  15360 // half 1
27 ; CHECK-NOFP16-LABEL:  Const1:
28 ; CHECK-NOFP16:        adrp x[[NUM:[0-9]+]], .[[LBL1]]
29 ; CHECK-NOFP16-NEXT:   ldr h0, [x[[NUM]], :lo12:.[[LBL1]]]
31 define half @Const2() {
32 entry:
33   ret half 0xH3000
35 ; CHECK-DAG-LABEL: Const2:
36 ; CHECK-DAG-NEXT:   fmov h0, #0.12500000
37 ; CHECK-DAG-NEXT:   ret
39 ; CHECK-NOFP16:        .[[LBL2:LCPI2_[0-9]]]:
40 ; CHECK-NOFP16-NEXT:   .hword  12288 // half 0.125
41 ; CHECK-NOFP16-LABEL:  Const2:
42 ; CHECK-NOFP16:        adrp x[[NUM:[0-9]+]], .[[LBL2]]
43 ; CHECK-NOFP16-NEXT:   ldr h0, [x[[NUM]], :lo12:.[[LBL2]]]
45 define half @Const3() {
46 entry:
47   ret half 0xH4F80
49 ; CHECK-DAG-LABEL: Const3:
50 ; CHECK-DAG-NEXT:   fmov h0, #30.00000000
51 ; CHECK-DAG-NEXT:   ret
53 ; CHECK-NOFP16:        .[[LBL3:LCPI3_[0-9]]]:
54 ; CHECK-NOFP16-NEXT:   .hword  20352 // half 30
55 ; CHECK-NOFP16-LABEL:  Const3:
56 ; CHECK-NOFP16:        adrp x[[NUM:[0-9]+]], .[[LBL3]]
57 ; CHECK-NOFP16-NEXT:   ldr h0, [x[[NUM]], :lo12:.[[LBL3]]]
60 define half @Const4() {
61 entry:
62   ret half 0xH4FC0
64 ; CHECK-DAG-LABEL: Const4:
65 ; CHECK-DAG-NEXT:  fmov h0, #31.00000000
66 ; CHECK-DAG-NEXT:  ret
68 ; CHECK-NOFP16:        .[[LBL4:LCPI4_[0-9]]]:
69 ; CHECK-NOFP16-NEXT:   .hword  20416                    // half 31
70 ; CHECK-NOFP16-LABEL:  Const4:
71 ; CHECK-NOFP16:        adrp x[[NUM:[0-9]+]], .[[LBL4]]
72 ; CHECK-NOFP16-NEXT:   ldr h0, [x[[NUM]], :lo12:.[[LBL4]]]
74 define half @Const5() {
75 entry:
76   ret half 0xH2FF0
78 ; CHECK-ILLEGAL:        .[[LBL5:LCPI5_[0-9]]]:
79 ; CHECK-ILLEGAL-NEXT:   .hword  12272                   // half 0.12402
80 ; CHECK-ILLEGAL-LABEL:  Const5:
81 ; CHECK-ILLEGAL:        adrp x[[NUM:[0-9]+]], .[[LBL5]]
82 ; CHECK-ILLEGAL-NEXT:   ldr h0, [x[[NUM]], :lo12:.[[LBL5]]]
84 define half @Const6() {
85 entry:
86   ret half 0xH4FC1
88 ; CHECK-ILLEGAL:        .[[LBL6:LCPI6_[0-9]]]:
89 ; CHECK-ILLEGAL-NEXT:   .hword  20417                   // half 31.016
90 ; CHECK-ILLEGAL-LABEL:  Const6:
91 ; CHECK-ILLEGAL:        adrp x[[NUM:[0-9]+]], .[[LBL6]]
92 ; CHECK-ILLEGAL-NEXT:   ldr h0, [x[[NUM]], :lo12:.[[LBL6]]]
95 define half @Const7() {
96 entry:
97   ret half 0xH5000
99 ; CHECK-ILLEGAL:        .[[LBL7:LCPI7_[0-9]]]:
100 ; CHECK-ILLEGAL-NEXT:   .hword  20480                   // half 32
101 ; CHECK-ILLEGAL-LABEL:  Const7:
102 ; CHECK-ILLEGAL:        adrp x[[NUM:[0-9]+]], .[[LBL7]]
103 ; CHECK-ILLEGAL-NEXT:   ldr h0, [x[[NUM]], :lo12:.[[LBL7]]]