1 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
2 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -arm-default-it | FileCheck %s
3 ; RUN: llc < %s -mtriple=thumbv8 -arm-no-restrict-it | FileCheck %s
4 ; RUN: llc < %s -mtriple=thumbv8 -arm-no-restrict-it -enable-tail-merge=0 | FileCheck %s
5 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
11 switch i32 %c, label %cond_next [
12 i32 1, label %cond_true
13 i32 7, label %cond_true
17 %tmp12 = add i32 %a, 1
18 %tmp1518 = add i32 %tmp12, %b
22 %tmp15 = add i32 %b, %a
26 define i32 @t2(i32 %a, i32 %b) nounwind {
29 ; CHECK: ite {{gt|le}}
32 %tmp1434 = icmp eq i32 %a, %b ; <i1> [#uses=1]
33 br i1 %tmp1434, label %bb17, label %bb.outer
35 bb.outer: ; preds = %cond_false, %entry
36 %b_addr.021.0.ph = phi i32 [ %b, %entry ], [ %tmp10, %cond_false ] ; <i32> [#uses=5]
37 %a_addr.026.0.ph = phi i32 [ %a, %entry ], [ %a_addr.026.0, %cond_false ] ; <i32> [#uses=1]
40 bb: ; preds = %cond_true, %bb.outer
41 %indvar = phi i32 [ 0, %bb.outer ], [ %indvar.next, %cond_true ] ; <i32> [#uses=2]
42 %tmp. = sub i32 0, %b_addr.021.0.ph ; <i32> [#uses=1]
43 %tmp.40 = mul i32 %indvar, %tmp. ; <i32> [#uses=1]
44 %a_addr.026.0 = add i32 %tmp.40, %a_addr.026.0.ph ; <i32> [#uses=6]
45 %tmp3 = icmp sgt i32 %a_addr.026.0, %b_addr.021.0.ph ; <i1> [#uses=1]
46 br i1 %tmp3, label %cond_true, label %cond_false
48 cond_true: ; preds = %bb
49 %tmp7 = sub i32 %a_addr.026.0, %b_addr.021.0.ph ; <i32> [#uses=2]
50 %tmp1437 = icmp eq i32 %tmp7, %b_addr.021.0.ph ; <i1> [#uses=1]
51 %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
52 br i1 %tmp1437, label %bb17, label %bb
54 cond_false: ; preds = %bb
55 %tmp10 = sub i32 %b_addr.021.0.ph, %a_addr.026.0 ; <i32> [#uses=2]
56 %tmp14 = icmp eq i32 %a_addr.026.0, %tmp10 ; <i1> [#uses=1]
57 br i1 %tmp14, label %bb17, label %bb.outer
59 bb17: ; preds = %cond_false, %cond_true, %entry
60 %a_addr.026.1 = phi i32 [ %a, %entry ], [ %tmp7, %cond_true ], [ %a_addr.026.0, %cond_false ] ; <i32> [#uses=1]
64 define i32 @t2_nomerge(i32 %a, i32 %b) nounwind {
66 ; CHECK-LABEL: t2_nomerge:
67 ; CHECK-NOT: ite {{gt|le}}
70 %tmp1434 = icmp eq i32 %a, %b ; <i1> [#uses=1]
71 br i1 %tmp1434, label %bb17, label %bb.outer
73 bb.outer: ; preds = %cond_false, %entry
74 %b_addr.021.0.ph = phi i32 [ %b, %entry ], [ %tmp10, %cond_false ] ; <i32> [#uses=5]
75 %a_addr.026.0.ph = phi i32 [ %a, %entry ], [ %a_addr.026.0, %cond_false ] ; <i32> [#uses=1]
78 bb: ; preds = %cond_true, %bb.outer
79 %indvar = phi i32 [ 0, %bb.outer ], [ %indvar.next, %cond_true ] ; <i32> [#uses=2]
80 %tmp. = sub i32 0, %b_addr.021.0.ph ; <i32> [#uses=1]
81 %tmp.40 = mul i32 %indvar, %tmp. ; <i32> [#uses=1]
82 %a_addr.026.0 = add i32 %tmp.40, %a_addr.026.0.ph ; <i32> [#uses=6]
83 %tmp3 = icmp sgt i32 %a_addr.026.0, %b_addr.021.0.ph ; <i1> [#uses=1]
84 br i1 %tmp3, label %cond_true, label %cond_false
86 cond_true: ; preds = %bb
87 %tmp7 = sub i32 %a_addr.026.0, %b_addr.021.0.ph ; <i32> [#uses=2]
88 %tmp1437 = icmp eq i32 %tmp7, %b_addr.021.0.ph ; <i1> [#uses=1]
89 %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
90 br i1 %tmp1437, label %bb17, label %bb
92 cond_false: ; preds = %bb
93 %tmp10 = sub i32 %b_addr.021.0.ph, %a_addr.026.0 ; <i32> [#uses=2]
94 %tmp14 = icmp eq i32 %b_addr.021.0.ph, %tmp10 ; <i1> [#uses=1]
95 br i1 %tmp14, label %bb17, label %bb.outer
97 bb17: ; preds = %cond_false, %cond_true, %entry
98 %a_addr.026.1 = phi i32 [ %a, %entry ], [ %tmp7, %cond_true ], [ %a_addr.026.0, %cond_false ] ; <i32> [#uses=1]
102 @x = external global i32* ; <i32**> [#uses=1]
104 define void @foo(i32 %a) nounwind {
106 %tmp = load i32*, i32** @x ; <i32*> [#uses=1]
107 store i32 %a, i32* %tmp
111 define void @t3(i32 %a, i32 %b) nounwind {
115 ; CHECK-NEXT: bxlt lr
117 ; CHECK: bl {{_?}}foo
118 %tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1]
119 br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock
121 cond_true: ; preds = %entry
122 call void @foo( i32 %b )
125 UnifiedReturnBlock: ; preds = %entry